From patchwork Tue Sep 19 10:53:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 815435 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xxKZk0Pf9z9sBZ for ; Tue, 19 Sep 2017 20:57:17 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 29404C21F44; Tue, 19 Sep 2017 10:56:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.9 required=5.0 tests=RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L4,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 963BCC21EFB; Tue, 19 Sep 2017 10:56:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 22406C21F3D; Tue, 19 Sep 2017 10:54:55 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.134]) by lists.denx.de (Postfix) with ESMTPS id E1BFEC21F19 for ; Tue, 19 Sep 2017 10:54:50 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.153]) by lucky1.263xmail.com (Postfix) with ESMTP id 58BE6163B; Tue, 19 Sep 2017 18:54:47 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 4BF983AA; Tue, 19 Sep 2017 18:54:44 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <3c5ef4fbd02198ee5ab6d911881cda49> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 857BXWEW6; Tue, 19 Sep 2017 18:54:47 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Date: Tue, 19 Sep 2017 18:53:15 +0800 Message-Id: <1505818405-49082-5-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> References: <1505818405-49082-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com Subject: [U-Boot] [U-Boot, v2, 04/14] clk: rockchip: Add SARADC clock support for rk3288 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu Reviewed-by: Philipp Tomsich Reviewed-by: Philipp Tomsich Acked-by: Philipp Tomsich --- Change in v2: - Use extract_bits. drivers/clk/rockchip/clk_rk3288.c | 41 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 478195b..a133810 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -111,6 +112,15 @@ enum { PERI_ACLK_DIV_SHIFT = 0, PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + /* + * CLKSEL24 + * saradc_div_con: + * clk_saradc=24MHz/(saradc_div_con+1) + */ + CLK_SARADC_DIV_CON_SHIFT = 8, + CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), + CLK_SARADC_DIV_CON_WIDTH = 8, + SOCSTS_DPLL_LOCK = 1 << 5, SOCSTS_APLL_LOCK = 1 << 6, SOCSTS_CPLL_LOCK = 1 << 7, @@ -634,6 +644,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, return rockchip_spi_get_clk(cru, gclk_rate, periph); } +static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) +{ + u32 div, val; + + val = readl(&cru->cru_clksel_con[24]); + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->cru_clksel_con[24], + CLK_SARADC_DIV_CON_MASK, + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); + + return rockchip_saradc_get_clk(cru); +} + static ulong rk3288_clk_get_rate(struct clk *clk) { struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); @@ -666,6 +701,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk) return gclk_rate; case PCLK_PWM: return PD_BUS_PCLK_HZ; + case SCLK_SARADC: + new_rate = rockchip_saradc_get_clk(priv->cru); + break; default: return -ENOENT; } @@ -756,6 +794,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) new_rate = rate; break; #endif + case SCLK_SARADC: + new_rate = rockchip_saradc_set_clk(priv->cru, rate); + break; default: return -ENOENT; }