| Message ID | 1505105281-2384-1-git-send-email-york.sun@nxp.com |
|---|---|
| State | Accepted |
| Commit | 42f43aa25876d1c77002ee5f333ab36dcb01d719 |
| Delegated to: | York Sun |
| Headers | show
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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR03MB2261 Cc: Albert Aribaud <albert.u.boot@aribaud.net>, Priyanka Jain <priyanka.jain@nxp.com>, Hou Zhiqiang <Zhiqiang.Hou@nxp.com>, Wenbin Song <wenbin.song@nxp.com> Subject: [U-Boot] [PATCH] armv8: fsl-layerscape: Add back L3 flushing for all exception levels X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <http://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> |
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[U-Boot] armv8: fsl-layerscape: Add back L3 flushing for all exception levels
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On 09/10/2017 09:48 PM, York Sun wrote: > CCN-504 HPF registers were believed to be accessible only from EL3. > However, recent tests proved otherwise. Remove checking for exception > level to re-enable L3 cache flushing for all levels. > > Signed-off-by: York Sun <york.sun@nxp.com> > --- Applied to fsl-qoriq master. York
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5ff01a0..fa93096 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -396,9 +396,6 @@ ENTRY(__asm_flush_l3_dcache) mov x29, lr mov x8, #0 - switch_el x0, 1f, 100f, 100f /* skip if not in EL3 */ - -1: dsb sy mov x0, #0x1 /* HNFPSTAT_SFONLY */ bl hnf_set_pstate @@ -416,7 +413,6 @@ ENTRY(__asm_flush_l3_dcache) bl hnf_pstate_poll cbz x0, 1f add x8, x8, #0x2 -100: 1: mov x0, x8 mov lr, x29
CCN-504 HPF registers were believed to be accessible only from EL3. However, recent tests proved otherwise. Remove checking for exception level to re-enable L3 cache flushing for all levels. Signed-off-by: York Sun <york.sun@nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 ---- 1 file changed, 4 deletions(-)