[U-Boot,01/19] configs: Add FPGA loadfs config for Arria 10

Message ID	1504003561-6290-2-git-send-email-tien.fong.chee@intel.com
State	Superseded
Delegated to:	Marek Vasut
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Tue, 29 Aug 2017 18:45:43 +0800 Message-Id: <1504003561-6290-2-git-send-email-tien.fong.chee@intel.com> In-Reply-To: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com> References: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, Ching Liang See <chin.liang.see@intel.com>, Tien Fong <skywindctf@gmail.com>, Westergteen Dalon <dalon.westergreen@intel.com> Subject: [U-Boot] [PATCH 01/19] configs: Add FPGA loadfs config for Arria 10 Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	Add FPGA, SDRAM drivers and booting to U-boot \| expand [U-Boot,00/19] Add FPGA, SDRAM drivers and booting to U-boot [U-Boot,01/19] configs: Add FPGA loadfs config for Arria 10 [U-Boot,02/19] configs: Add FAT fs support for SPL [U-Boot,03/19] arm: socfpga: Add driver for flash to program FPGA [U-Boot,04/19] arm: socfpga: Add FPGA loadfs command support [U-Boot,05/19] arm: socfpga: Enhance FPGA program support with at least 4 byte data [U-Boot,06/19] arm: socfpga: Rename the gen5 sdram driver to more specific name [U-Boot,07/19] arm: socfpga: Add DRAM bank size initialization function [U-Boot,08/19] arm: socfpga: Add COMPAT macro for Network on Chip(NoC) [U-Boot,09/19] arm: socfpga: Add DDR driver for Arria 10 [U-Boot,10/19] configs: Add DDR Kconfig support for Arria 10 [U-Boot,11/19] arm: socfpga: Enable build for DDR Arria 10 [U-Boot,12/19] doc: dtbinding: Add Intel Arria 10 SoCFPGA chosen binding [U-Boot,13/19] dts: Add the FPGA design file name to DTS [U-Boot,14/19] dts: Add device storage and partition to DTS [U-Boot,15/19] arm: socfpga: Add support to memory allocation in SPL [U-Boot,16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 [U-Boot,17/19] arm: socfpga: Adding clock frequency info for U-boot [U-Boot,18/19] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot [U-Boot,19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

Message ID

1504003561-6290-2-git-send-email-tien.fong.chee@intel.com

State

Superseded

Delegated to:

Marek Vasut

Headers

From: tien.fong.chee@intel.com
To: u-boot@lists.denx.de
Date: Tue, 29 Aug 2017 18:45:43 +0800
Message-Id: <1504003561-6290-2-git-send-email-tien.fong.chee@intel.com>
In-Reply-To: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>
References: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, 
	Ching Liang See <chin.liang.see@intel.com>,
	Tien Fong <skywindctf@gmail.com>, 
	Westergteen Dalon <dalon.westergreen@intel.com>
Subject: [U-Boot] [PATCH 01/19] configs: Add FPGA loadfs config for Arria 10
Precedence: list
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
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Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

Add FPGA, SDRAM drivers and booting to U-boot | expand

Commit Message

Chee, Tien Fong Aug. 29, 2017, 10:45 a.m. UTC

From: Tien Fong Chee <tien.fong.chee@intel.com>

This config allow FPGA design loaded from FAT fs to FPGA manager.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 configs/socfpga_arria10_defconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

Comments

Marek Vasut Aug. 29, 2017, 11:51 a.m. UTC | #1

On 08/29/2017 12:45 PM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> This config allow FPGA design loaded from FAT fs to FPGA manager.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  configs/socfpga_arria10_defconfig |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
> index 53ab66f..d555743 100644
> --- a/configs/socfpga_arria10_defconfig
> +++ b/configs/socfpga_arria10_defconfig
> @@ -29,3 +29,4 @@ CONFIG_DWAPB_GPIO=y
>  CONFIG_DM_MMC=y
>  CONFIG_SYS_NS16550=y
>  CONFIG_USE_TINY_PRINTF=y
> +CONFIG_CMD_FPGA_LOADFS=y

You should enable stuff only after you add the necessary support bits ...

Chee, Tien Fong Aug. 30, 2017, 5:59 a.m. UTC | #2

On Sel, 2017-08-29 at 13:51 +0200, Marek Vasut wrote:
> On 08/29/2017 12:45 PM, tien.fong.chee@intel.com wrote:

> > 

> > From: Tien Fong Chee <tien.fong.chee@intel.com>

> > 

> > This config allow FPGA design loaded from FAT fs to FPGA manager.

> > 

> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

> > ---

> >  configs/socfpga_arria10_defconfig |    1 +

> >  1 files changed, 1 insertions(+), 0 deletions(-)

> > 

> > diff --git a/configs/socfpga_arria10_defconfig

> > b/configs/socfpga_arria10_defconfig

> > index 53ab66f..d555743 100644

> > --- a/configs/socfpga_arria10_defconfig

> > +++ b/configs/socfpga_arria10_defconfig

> > @@ -29,3 +29,4 @@ CONFIG_DWAPB_GPIO=y

> >  CONFIG_DM_MMC=y

> >  CONFIG_SYS_NS16550=y

> >  CONFIG_USE_TINY_PRINTF=y

> > +CONFIG_CMD_FPGA_LOADFS=y

> You should enable stuff only after you add the necessary support bits

> ...

> 

I enabled it as early as possible, because i would like to use
compiling for detecting any code errors while adding the neccesssary
support bits. I can rearrange the patches sequence.

Marek Vasut Aug. 30, 2017, 8:45 a.m. UTC | #3

On 08/30/2017 07:59 AM, Chee, Tien Fong wrote:
> On Sel, 2017-08-29 at 13:51 +0200, Marek Vasut wrote:
>> On 08/29/2017 12:45 PM, tien.fong.chee@intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> This config allow FPGA design loaded from FAT fs to FPGA manager.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> ---
>>>  configs/socfpga_arria10_defconfig |    1 +
>>>  1 files changed, 1 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/configs/socfpga_arria10_defconfig
>>> b/configs/socfpga_arria10_defconfig
>>> index 53ab66f..d555743 100644
>>> --- a/configs/socfpga_arria10_defconfig
>>> +++ b/configs/socfpga_arria10_defconfig
>>> @@ -29,3 +29,4 @@ CONFIG_DWAPB_GPIO=y
>>>  CONFIG_DM_MMC=y
>>>  CONFIG_SYS_NS16550=y
>>>  CONFIG_USE_TINY_PRINTF=y
>>> +CONFIG_CMD_FPGA_LOADFS=y
>> You should enable stuff only after you add the necessary support bits
>> ...
>>
> I enabled it as early as possible, because i would like to use
> compiling for detecting any code errors while adding the neccesssary
> support bits. I can rearrange the patches sequence.
> 
Except you enable feature which cannot work, so this is wrong. If you
need this for debugging purposes, great, but in the series it should go
after the groundwork is laid.

Chee, Tien Fong Sept. 4, 2017, 5:29 a.m. UTC | #4

On Rab, 2017-08-30 at 10:45 +0200, Marek Vasut wrote:
> On 08/30/2017 07:59 AM, Chee, Tien Fong wrote:

> > 

> > On Sel, 2017-08-29 at 13:51 +0200, Marek Vasut wrote:

> > > 

> > > On 08/29/2017 12:45 PM, tien.fong.chee@intel.com wrote:

> > > > 

> > > > 

> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>

> > > > 

> > > > This config allow FPGA design loaded from FAT fs to FPGA

> > > > manager.

> > > > 

> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

> > > > ---

> > > >  configs/socfpga_arria10_defconfig |    1 +

> > > >  1 files changed, 1 insertions(+), 0 deletions(-)

> > > > 

> > > > diff --git a/configs/socfpga_arria10_defconfig

> > > > b/configs/socfpga_arria10_defconfig

> > > > index 53ab66f..d555743 100644

> > > > --- a/configs/socfpga_arria10_defconfig

> > > > +++ b/configs/socfpga_arria10_defconfig

> > > > @@ -29,3 +29,4 @@ CONFIG_DWAPB_GPIO=y

> > > >  CONFIG_DM_MMC=y

> > > >  CONFIG_SYS_NS16550=y

> > > >  CONFIG_USE_TINY_PRINTF=y

> > > > +CONFIG_CMD_FPGA_LOADFS=y

> > > You should enable stuff only after you add the necessary support

> > > bits

> > > ...

> > > 

> > I enabled it as early as possible, because i would like to use

> > compiling for detecting any code errors while adding the

> > neccesssary

> > support bits. I can rearrange the patches sequence.

> > 

> Except you enable feature which cannot work, so this is wrong. If you

> need this for debugging purposes, great, but in the series it should

> go

> after the groundwork is laid.

> 

Okay, i will reorder the series of patches.

diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 53ab66f..d555743 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -29,3 +29,4 @@  CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_FPGA_LOADFS=y

[U-Boot,01/19] configs: Add FPGA loadfs config for Arria 10

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