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[U-Boot,16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10

Message ID 1504003561-6290-17-git-send-email-tien.fong.chee@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series Add FPGA, SDRAM drivers and booting to U-boot | expand

Commit Message

Chee, Tien Fong Aug. 29, 2017, 10:45 a.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

Enhance preloader header with both additional program length and program
entry offset attributes, which offset is relative to the start of program
header.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/include/mach/boot0.h |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)
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Patch

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
index 22d9e7f..94480b4 100644
--- a/arch/arm/mach-socfpga/include/mach/boot0.h
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -11,8 +11,13 @@ 
 	.balignl 64,0xf33db33f;
 
 	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
-	.word	0xc01df00d;	/* Version, flags, length */
-	.word	0xcafec0d3;	/* Checksum, zero-pad */
+	.word	0xc01df00d; /* Header length(2B),flags(1B),version(1B) */
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+	.word	0xfeedface; /* Program length(4B) */
+	.word	0xf00dcafe; /* Program entry offset(4B),relative to  */
+						/* the start of program header */
+#endif
+	.word	0xcafec0d3;	/* Simple checksum(2B),spare offset(2B) */
 	nop;
 
 	b reset;		/* SoCFPGA jumps here */