diff mbox series

[U-Boot,13/19] dts: Add the FPGA design file name to DTS

Message ID	1504003561-6290-14-git-send-email-tien.fong.chee@intel.com
State	Superseded
Delegated to:	Marek Vasut
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Tue, 29 Aug 2017 18:45:55 +0800 Message-Id: <1504003561-6290-14-git-send-email-tien.fong.chee@intel.com> In-Reply-To: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com> References: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, Ching Liang See <chin.liang.see@intel.com>, Tien Fong <skywindctf@gmail.com>, Westergteen Dalon <dalon.westergreen@intel.com> Subject: [U-Boot] [PATCH 13/19] dts: Add the FPGA design file name to DTS Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	Add FPGA, SDRAM drivers and booting to U-boot \| expand [U-Boot,00/19] Add FPGA, SDRAM drivers and booting to U-boot [U-Boot,01/19] configs: Add FPGA loadfs config for Arria 10 [U-Boot,02/19] configs: Add FAT fs support for SPL [U-Boot,03/19] arm: socfpga: Add driver for flash to program FPGA [U-Boot,04/19] arm: socfpga: Add FPGA loadfs command support [U-Boot,05/19] arm: socfpga: Enhance FPGA program support with at least 4 byte data [U-Boot,06/19] arm: socfpga: Rename the gen5 sdram driver to more specific name [U-Boot,07/19] arm: socfpga: Add DRAM bank size initialization function [U-Boot,08/19] arm: socfpga: Add COMPAT macro for Network on Chip(NoC) [U-Boot,09/19] arm: socfpga: Add DDR driver for Arria 10 [U-Boot,10/19] configs: Add DDR Kconfig support for Arria 10 [U-Boot,11/19] arm: socfpga: Enable build for DDR Arria 10 [U-Boot,12/19] doc: dtbinding: Add Intel Arria 10 SoCFPGA chosen binding [U-Boot,13/19] dts: Add the FPGA design file name to DTS [U-Boot,14/19] dts: Add device storage and partition to DTS [U-Boot,15/19] arm: socfpga: Add support to memory allocation in SPL [U-Boot,16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 [U-Boot,17/19] arm: socfpga: Adding clock frequency info for U-boot [U-Boot,18/19] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot [U-Boot,19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot

Commit Message

Chee, Tien Fong Aug. 29, 2017, 10:45 a.m. UTC

From: Tien Fong Chee <tien.fong.chee@intel.com>

During FPGA program, FPGA raw binary data file would be searched from
flash based on the file name defined in DTS, and then feeding the FPGA
file found from flash into FPGA manager for configuring FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi   |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
index d10e089..b6b2f75 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
@@ -20,8 +20,8 @@ 
 
 	chosen {
 		/* Bootloader setting: uboot.rbf_filename */
-		cff-file = "ghrd_10as066n2.periph.rbf";
-		early-release-fpga-config;
+		cff-file = "ghrd_10as066n2.periph.rbf.mkimage";
+		cffcore-file = "ghrd_10as066n2.core.rbf.mkimage";
 	};
 
 	soc {