From patchwork Mon Jul 31 10:50:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 795696 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xLbqW39ZTz9s03 for ; Mon, 31 Jul 2017 20:51:51 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 36D6EC22131; Mon, 31 Jul 2017 10:51:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A47B0C2215F; Mon, 31 Jul 2017 10:50:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2AE96C220B8; Mon, 31 Jul 2017 10:50:39 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lists.denx.de (Postfix) with ESMTPS id A3D2FC2207C for ; Mon, 31 Jul 2017 10:50:34 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 31 Jul 2017 03:50:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,442,1496127600"; d="scan'208";a="113861734" Received: from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com, ) ([10.255.137.189]) by orsmga004.jf.intel.com with ESMTP; 31 Jul 2017 03:50:31 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Mon, 31 Jul 2017 18:50:19 +0800 Message-Id: <1501498222-9422-3-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501498222-9422-1-git-send-email-tien.fong.chee@intel.com> References: <1501498222-9422-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Tien Fong , Westergteen Dalon Subject: [U-Boot] [PATCH 2/5] arm: socfpga: Add checking function on FPGA setting in FDT X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Function for checking FPGA early release setting which is defined by user in FDT chosen section. This function would be used by later driver in decision applying appropriate FPGA configuration in early release or full FPGA booting mode. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc_arria10.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index b219aac..a8167eb 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -44,6 +44,7 @@ static inline void socfpga_fpga_add(void) {} unsigned int dedicated_uart_com_port(const void *blob); unsigned int shared_uart_com_port(const void *blob); unsigned int uart_com_port(const void *blob); +int is_early_release_fpga_config(const void *blob); u32 boot_device(void); #endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 069a0a6..b9a8693 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -235,6 +235,26 @@ unsigned int uart_com_port(const void *blob) return shared_uart_com_port(blob); } +int is_chosen_boolean_true(const void *blob, const char *name) +{ + int node; + int rval = 0; + + node = fdt_subnode_offset(blob, 0, "chosen"); + + if (node >= 0) + rval = fdtdec_get_bool(blob, node, name); + + return rval; +} + +int is_early_release_fpga_config(const void *blob) +{ + static const char *name = "early-release-fpga-config"; + + return is_chosen_boolean_true(blob, name); +} + u32 boot_device(void) { const u32 bsel = readl(&sysmgr_regs->bootinfo);