From patchwork Wed Jun 21 08:31:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: stefanc@malvell.com X-Patchwork-Id: 778816 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wt3hW5fJ2z9s0g for ; Wed, 21 Jun 2017 22:20:43 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 8EB7DC21C6E; Wed, 21 Jun 2017 12:14:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 40226C21CCC; Wed, 21 Jun 2017 12:12:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 21898C21CA6; Wed, 21 Jun 2017 08:35:28 +0000 (UTC) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lists.denx.de (Postfix) with ESMTPS id A3DADC21CA3 for ; Wed, 21 Jun 2017 08:35:23 +0000 (UTC) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v5L8UP8t017563; Wed, 21 Jun 2017 01:35:15 -0700 Received: from il-exch01.marvell.com ([199.203.130.101]) by mx0a-0016f401.pphosted.com with ESMTP id 2b6cq7pw9p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2017 01:35:15 -0700 Received: from SC-EXCH02.marvell.com (10.93.176.82) by IL-EXCH01.marvell.com (10.4.102.220) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 21 Jun 2017 11:35:12 +0300 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 21 Jun 2017 01:35:11 -0700 Received: from stefanc.pt.marvell.com (unknown [10.5.24.120]) by maili.marvell.com (Postfix) with ESMTP id 383FA3F7041; Wed, 21 Jun 2017 01:35:10 -0700 (PDT) From: To: Date: Wed, 21 Jun 2017 11:31:31 +0300 Message-ID: <1498033898-15650-4-git-send-email-stefanc@malvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498033898-15650-1-git-send-email-stefanc@malvell.com> References: <1498033898-15650-1-git-send-email-stefanc@malvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-06-21_01:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706210143 X-Mailman-Approved-At: Wed, 21 Jun 2017 12:12:02 +0000 Cc: stefanc@malvell.com, joe.hershberger@ni.com, sr@denx.de, igall@marvell.com Subject: [U-Boot] [PATCH 03/10] net: mvpp2x: Enable GoP packet padding in TX X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Chulski This patch enable padding of packets shorter than 64B in TX(set by default). Disabling of padding cause crushes on MACCIATO board. Regarding to GoP instruction padding should be enabled. Change-Id: Iceaa1bd8a3543795463938d1a8d561f4ecc29234 Signed-off-by: Stefan Chulski Reviewed-on: http://vgitil04.il.marvell.com:8080/39270 Tested-by: iSoC Platform CI Reviewed-by: Igal Liberman --- drivers/net/mvpp2.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 1264f14..3083111 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -3063,10 +3063,6 @@ static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port) val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK; writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); - val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); - val |= MVPP2_GMAC_PORT_DIS_PADING_MASK; - writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); - val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); /* * Configure GIG MAC to 1000Base-X mode connected to a fiber @@ -3109,10 +3105,6 @@ static void gop_gmac_sgmii_cfg(struct mvpp2_port *port) val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK; writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); - val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); - val |= MVPP2_GMAC_PORT_DIS_PADING_MASK; - writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); - val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); /* configure GIG MAC to SGMII mode */ val &= ~MVPP2_GMAC_PORT_TYPE_MASK; @@ -3151,10 +3143,6 @@ static void gop_gmac_rgmii_cfg(struct mvpp2_port *port) val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK; writel(val, port->base + MVPP2_GMAC_CTRL_4_REG); - val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); - val &= ~MVPP2_GMAC_PORT_DIS_PADING_MASK; - writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); - val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); /* configure GIG MAC to SGMII mode */ val &= ~MVPP2_GMAC_PORT_TYPE_MASK;