From patchwork Sun Apr 23 09:17:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: igall@marvell.com X-Patchwork-Id: 754526 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wBhvW0TMmz9s8V for ; Tue, 25 Apr 2017 09:12:39 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B7A3FC21C3A; Mon, 24 Apr 2017 23:03:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D7714C21CA5; Mon, 24 Apr 2017 22:58:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 28013C21C39; Sun, 23 Apr 2017 09:19:36 +0000 (UTC) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lists.denx.de (Postfix) with ESMTPS id 7D36EC21C1F for ; Sun, 23 Apr 2017 09:19:35 +0000 (UTC) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v3N9FHq2029006; Sun, 23 Apr 2017 02:19:32 -0700 Received: from il-exch02.marvell.com ([199.203.130.102]) by mx0a-0016f401.pphosted.com with ESMTP id 2a04hk3ktu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 23 Apr 2017 02:19:31 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by IL-EXCH02.marvell.com (10.4.102.221) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Sun, 23 Apr 2017 12:19:27 +0300 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Sun, 23 Apr 2017 02:19:27 -0700 Received: from igall-OptiPlex-990.pt.marvell.com (unknown [10.5.24.64]) by maili.marvell.com (Postfix) with ESMTP id 724283F7040; Sun, 23 Apr 2017 02:19:25 -0700 (PDT) From: To: Date: Sun, 23 Apr 2017 12:17:31 +0300 Message-ID: <1492939057-4724-8-git-send-email-igall@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1492939057-4724-1-git-send-email-igall@marvell.com> References: <1492939057-4724-1-git-send-email-igall@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-23_08:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1704230165 X-Mailman-Approved-At: Mon, 24 Apr 2017 22:58:32 +0000 Cc: Hanna Hawa , nadavh@marvell.com, neta@marvell.com, sr@denx.de, Igal Liberman Subject: [U-Boot] [PATCH 07/13] fix: phy: marvell: comphy: cp110: update comphy selector option X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Roese Align PHY selectors register with Armada-CP-110 functional SPEC update all relevant device trees with this change. Change-Id: I4384eb561ec6a7e02e7fa701626ad81fd6e10f1c Signed-off-by: Hanna Hawa Signed-off-by: Stefan Roese Signed-off-by: Igal Liberman --- arch/arm/dts/armada-7040-db.dts | 2 +- arch/arm/dts/armada-8040-mcbin.dts | 4 ++-- drivers/phy/marvell/comphy_cp110.c | 29 +++++++++++++---------------- 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index 84e0dbd..5fa2876 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -158,7 +158,7 @@ &cpm_comphy { phy0 { - phy-type = ; + phy-type = ; phy-speed = ; }; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index dde495a..991ddc0 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -264,7 +264,7 @@ &cps_comphy { /* * CP1 Serdes Configuration: - * Lane 0: SGMII2 + * Lane 0: SGMII1 * Lane 1: SATA 0 * Lane 2: USB HOST 0 * Lane 3: SATA1 @@ -272,7 +272,7 @@ * Lane 5: SGMII3 */ phy0 { - phy-type = ; + phy-type = ; phy-speed = ; }; phy1 { diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index a4dddb8..6a6083b 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -37,23 +37,20 @@ struct utmi_phy_data { * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI) */ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */ - {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, /* Lane 1 */ - {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ + {PHY_TYPE_SATA1, 0x4} } }, + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ + {PHY_TYPE_SATA0, 0x4} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_XAUI1, 0x1}, - {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x2}, - {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */ - {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, - {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, + {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, + {PHY_TYPE_SATA0, 0x4} } }, + {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ + {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, + {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 4 */ + {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, + {PHY_TYPE_SGMII1, 0x2} } }, + {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ + {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, }; struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {