From patchwork Wed Mar 22 09:54:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 741943 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3vp4r506X1z9s7H for ; Wed, 22 Mar 2017 20:58:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BDA42C21CFF; Wed, 22 Mar 2017 09:56:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0D4C6C21CE0; Wed, 22 Mar 2017 09:54:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0376DC21CF3; Wed, 22 Mar 2017 09:54:33 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id AB634C21C9C for ; Wed, 22 Mar 2017 09:54:28 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id v2M9knUi001586; Wed, 22 Mar 2017 10:54:24 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 29b9wgut36-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 22 Mar 2017 10:54:24 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0B8D23D; Wed, 22 Mar 2017 09:54:24 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E52C02644; Wed, 22 Mar 2017 09:54:23 +0000 (GMT) Received: from localhost (10.75.127.49) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Wed, 22 Mar 2017 10:54:23 +0100 From: To: , , , , Date: Wed, 22 Mar 2017 10:54:08 +0100 Message-ID: <1490176456-24813-7-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490176456-24813-1-git-send-email-patrice.chotard@st.com> References: <1490176456-24813-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.49] X-ClientProxiedBy: SFHDAG3NODE2.st.com (10.75.127.8) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-22_08:, , signatures=0 Cc: christophe.kerello@st.com, patrick.delaunay@st.com Subject: [U-Boot] [PATCH v2 06/14] usb: ehci: Add STi ehci support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Add support for on-chip ehci controller available on STMicrolectronics SoCs. ehci support will be then available on both type A USB 2.0 connectors. Signed-off-by: Patrice Chotard Reviewed-by: Simon Glass --- v2: _ update error messages _ add remove callback to put core into reset drivers/usb/host/Kconfig | 9 ++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-sti.c | 115 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 drivers/usb/host/ehci-sti.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 5129a57..d66f49e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -120,6 +120,15 @@ config USB_EHCI_MSM This driver supports combination of Chipidea USB controller and Synapsys USB PHY in host mode only. +config USB_EHCI_STI + bool "Support for STMicroelectronics on-chip EHCI USB controller" + depends on ARCH_STI + select STI_PHY_USB + default y + ---help--- + Enables support for the on-chip EHCI controller on + STMicroelectronics SoCs. + config USB_EHCI_ZYNQ bool "Support for Xilinx Zynq on-chip EHCI USB controller" depends on ARCH_ZYNQ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 58c0cf5..303aa32 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o +obj-$(CONFIG_USB_EHCI_STI) += ehci-sti.o obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o diff --git a/drivers/usb/host/ehci-sti.c b/drivers/usb/host/ehci-sti.c new file mode 100644 index 0000000..390709d --- /dev/null +++ b/drivers/usb/host/ehci-sti.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2017 + * Patrice Chotard + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "ehci.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct sti_ehci_priv { + struct ehci_ctrl ctrl; + struct reset_ctl power_ctl; + struct reset_ctl softreset_ctl; +}; + +static int sti_ehci_probe(struct udevice *dev) +{ + struct sti_ehci_priv *priv = dev_get_priv(dev); + struct ehci_hccr *hccr = priv->ctrl.hccr; + struct ehci_hcor *hcor; + struct udevice *dev_phy; + int ret, phy_node; + + hccr = (struct ehci_hccr *)dev_get_addr(dev); + + if (hccr == (void *)FDT_ADDR_T_NONE) + return -EINVAL; + + ret = reset_get_by_name(dev, "power", &priv->power_ctl); + if (ret) { + error("can't get power for %s (%d)", dev->name, ret); + return ret; + } + + ret = reset_get_by_name(dev, "softreset", &priv->softreset_ctl); + if (ret) { + error("can't get soft reset for %s (%d)", dev->name, ret); + return ret; + } + + ret = reset_deassert(&priv->softreset_ctl); + if (ret < 0) { + error("EHCI soft reset deassert failed: %d", ret); + return ret; + } + + ret = reset_deassert(&priv->power_ctl); + if (ret < 0) { + error("EHCI power deassert failed: %d", ret); + return ret; + } + + /* get phy node */ + phy_node = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phys"); + if (phy_node <= 0) { + error("USB PHY DT node not found.\n"); + return -ENODEV; + } + + /* probe associated phy */ + ret = uclass_get_device_by_of_offset(UCLASS_MISC, phy_node, &dev_phy); + + hcor = (struct ehci_hcor *)((phys_addr_t)hccr + + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); + + return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); +} + +static int sti_ehci_remove(struct udevice *dev) +{ + struct sti_ehci_priv *priv = dev_get_priv(dev); + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + ret = reset_assert(&priv->power_ctl); + if (ret < 0) { + error("EHCI power assert failed: %d", ret); + return ret; + } + + ret = reset_assert(&priv->softreset_ctl); + if (ret < 0) { + error("EHCI soft reset assert failed: %d", ret); + return ret; + } + + return 0; +} + +static const struct udevice_id sti_usb_ids[] = { + { .compatible = "st,st-ehci-300x" }, + { } +}; + +U_BOOT_DRIVER(ehci_sti) = { + .name = "ehci_sti", + .id = UCLASS_USB, + .of_match = sti_usb_ids, + .probe = sti_ehci_probe, + .remove = sti_ehci_remove, + .ops = &ehci_usb_ops, + .priv_auto_alloc_size = sizeof(struct sti_ehci_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +};