From patchwork Mon Feb 20 09:31:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 729854 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3vRdjP4BX1z9s85 for ; Mon, 20 Feb 2017 20:33:29 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9BBDCB38DE; Mon, 20 Feb 2017 10:33:27 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mkyc-ovBLLPb; Mon, 20 Feb 2017 10:33:27 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A95E9B390A; Mon, 20 Feb 2017 10:32:58 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 396B1A7BD2 for ; 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Mon, 20 Feb 2017 09:31:54 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 226FE240B; Mon, 20 Feb 2017 09:31:54 +0000 (GMT) Received: from localhost (10.75.127.45) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Mon, 20 Feb 2017 10:31:53 +0100 From: To: , , , Date: Mon, 20 Feb 2017 10:31:42 +0100 Message-ID: <1487583109-13147-3-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1487583109-13147-1-git-send-email-patrice.chotard@st.com> References: <1487583109-13147-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG5NODE3.st.com (10.75.127.15) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-20_06:, , signatures=0 Cc: christophe.kerello@st.com, patrick.delaunay@st.com Subject: [U-Boot] [PATCH v5 2/9] STiH410: Add STi timer driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Add ARM global timer based timer Signed-off-by: Patrice Chotard Reviewed-by: Simon Glass --- drivers/timer/Kconfig | 7 +++++ drivers/timer/Makefile | 1 + drivers/timer/sti-timer.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) create mode 100644 drivers/timer/sti-timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index cd38a6d..72c1416 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -58,4 +58,11 @@ config AST_TIMER This is mostly because they all share several registers which makes it difficult to completely separate them. +config STI_TIMER + bool "STi timer support" + depends on TIMER + default y if ARCH_STI + help + Select this to enable a timer for STi devices. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index a4b1a48..ae94be8 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o +obj-$(CONFIG_STI_TIMER) += sti-timer.o diff --git a/drivers/timer/sti-timer.c b/drivers/timer/sti-timer.c new file mode 100644 index 0000000..e1419c4 --- /dev/null +++ b/drivers/timer/sti-timer.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2017 Patrice Chotard + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct sti_timer_priv { + struct globaltimer *global_timer; +}; + +static int sti_timer_get_count(struct udevice *dev, u64 *count) +{ + struct sti_timer_priv *priv = dev_get_priv(dev); + struct globaltimer *global_timer = priv->global_timer; + u32 low, high; + u64 timer; + u32 old = readl(&global_timer->cnt_h); + + while (1) { + low = readl(&global_timer->cnt_l); + high = readl(&global_timer->cnt_h); + if (old == high) + break; + else + old = high; + } + timer = high; + *count = (u64)((timer << 32) | low); + + return 0; +} + +static int sti_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct sti_timer_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + + uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + + /* get arm global timer base address */ + addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg"); + priv->global_timer = (struct globaltimer *)addr; + + /* init timer */ + writel(0x01, &priv->global_timer->ctl); + + return 0; +} + +static const struct timer_ops sti_timer_ops = { + .get_count = sti_timer_get_count, +}; + +static const struct udevice_id sti_timer_ids[] = { + { .compatible = "arm,cortex-a9-global-timer" }, + {} +}; + +U_BOOT_DRIVER(sti_timer) = { + .name = "sti_timer", + .id = UCLASS_TIMER, + .of_match = sti_timer_ids, + .priv_auto_alloc_size = sizeof(struct sti_timer_priv), + .probe = sti_timer_probe, + .ops = &sti_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +};