From patchwork Sun Feb 19 04:07:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dalon Westergreen X-Patchwork-Id: 729790 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3vRcT96mxJz9s86 for ; Mon, 20 Feb 2017 19:37:49 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="eSsQsrqg"; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6177BB3984; Mon, 20 Feb 2017 09:27:25 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tzWt9fC6ll7M; Mon, 20 Feb 2017 09:27:25 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6E95CB3BBC; Mon, 20 Feb 2017 09:20:26 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2236D4A068 for ; Sun, 19 Feb 2017 05:08:15 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id g_EvtgLK7M-P for ; Sun, 19 Feb 2017 05:08:15 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pg0-f66.google.com (mail-pg0-f66.google.com [74.125.83.66]) by theia.denx.de (Postfix) with ESMTPS id 9832F4A026 for ; Sun, 19 Feb 2017 05:08:10 +0100 (CET) Received: by mail-pg0-f66.google.com with SMTP id 1so1334188pgz.2 for ; Sat, 18 Feb 2017 20:08:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=F9djy0RjLzn14T9mvLCvgrjVY7ZY9fh2N+m6GDSEYfw=; b=eSsQsrqgzKOB960mGl7T5g7Gdl5DDcTTOmu5EAUvJ6xQ6PXqrwoPJZE2/1kNtXC+in ySADEv/fH8zaV/yAPVQkdX2mSSjIsgC1ylQfKCEdyIUobK7PdN7uJAs360971u3yW5CA mvhBiRlOZ+ts6fanAH3WFIW66VJEV3t+eX51xli0gERK5hdTftyiMgZHSIw9Z8w9436J l+xigopd4+v1sBsjLi0qdRAHZbR+OO+Wp5crzmHLOjFo3bTkRUT/ew4yfPKZwlSrMGk2 te6lnkeGO7RuRDCE3CN/Kpi5CoeU/gECABDQwOedwmRdiUNYz2hKucXlINxgO0Tg6AfX +hzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F9djy0RjLzn14T9mvLCvgrjVY7ZY9fh2N+m6GDSEYfw=; b=t4PuMvXA6DcbzYWzH1sAx9ebfFkRGx6UrKn6DEylhzcqi5EV8N06hgcAD48QZ00qgk QqjTNe+eSxkPbqiZOkCIC/x4OukuefkB0EoBdYlnXVaiVsixEN3AvxADa+91rltjBtgC 1qJgR+7c4a3wwki8f/QZct2hFdKd7nBYgW1byoDgbYi+2f55LU1fGaOzYqsctpgFNoqE Pyhl14OKabn76gW1JrnbFIkvHvSYOE2Wf7Q1vc0iuoriwb7H8/qM6nk+WtX8IzNvqn6u 2ljAJeU0Zxyq6+QfYlaO5RnwPNPGxGdoPY1JNsJefkJivGWk7/+RFVlSSm0lPTQB5ZTO Z2uA== X-Gm-Message-State: AMke39l2hM0pHqhntl5mu663wjftESW50ujnz2JOZSSsTIgAfS//JcEym1rKGlBXNmfHnw== X-Received: by 10.84.175.132 with SMTP id t4mr22177843plb.38.1487477289151; Sat, 18 Feb 2017 20:08:09 -0800 (PST) Received: from dwesterg-mobl1.amr.corp.intel.com ([134.134.139.76]) by smtp.gmail.com with ESMTPSA id q26sm3979814pfg.47.2017.02.18.20.08.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 18 Feb 2017 20:08:08 -0800 (PST) From: Dalon Westergreen To: u-boot@lists.denx.de, marex@denx.de, chin.liang.see@intel.com, dinguyen@kernel.org, sr@denx.de, mailinglists@kunz-im-inter.net, agust@denx.de, tien.fong.chee@intel.com Date: Sat, 18 Feb 2017 20:07:53 -0800 Message-Id: <1487477280-21077-2-git-send-email-dwesterg@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487477280-21077-1-git-send-email-dwesterg@gmail.com> References: <1487477280-21077-1-git-send-email-dwesterg@gmail.com> Subject: [U-Boot] [PATCH v3 1/8] arm: socfpga: Add distro boot to socfpga common header X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a common environment and support for distro boot in the common socfpga header. Signed-off-by: Dalon Westergreen --- Changes in v3: - fix spacing between asterix - remove verify=n as a default setting Changes in v2: - Remove unneeded CONFIG_BOOTFILE and fdt_addr - cleanup spacing in MMC env size --- include/configs/socfpga_common.h | 52 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 582b04a..f702ed1 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -67,6 +67,9 @@ #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD #endif +#define CONFIG_CMD_PXE +#define CONFIG_MENU + /* * Cache */ @@ -245,13 +248,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * U-Boot environment */ #if !defined(CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_SIZE (8 * 1024) #endif /* Environment for SDMMC boot */ #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ #endif /* Environment for QSPI boot */ @@ -308,8 +311,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#endif +#else +#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 #endif #endif @@ -331,4 +338,41 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +/* Extra Environment */ +#ifndef CONFIG_SPL_BUILD +#include + +#ifdef CONFIG_CMD_PXE +#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_PXE(func) \ + func(DHCP, dhcp, na) + +#include + +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0xa000000\0" \ + "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "fdt_addr_r=0x02000000\0" \ + "scriptaddr=0x02100000\0" \ + "pxefile_addr_r=0x02200000\0" \ + "ramdisk_addr_r=0x02300000\0" \ + BOOTENV + +#endif +#endif + #endif /* __CONFIG_SOCFPGA_COMMON_H__ */