diff mbox

[U-Boot] mpc85xx: Use symbolic names for cache control bits

Message ID 1485268823-30996-1-git-send-email-thomas.graziadei@omicronenergy.com
State Accepted
Commit 2ec70961e7dc6548451822857aca5dc2573cee55
Delegated to: York Sun
Headers show

Commit Message

thomas.graziadei@omicronenergy.com Jan. 24, 2017, 2:40 p.m. UTC 
From: Mark Marshall <Mark.Marshall@omicron.at>

We should use the symbolic names for the cache control bits.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com>
---
 arch/powerpc/cpu/mpc85xx/start.S | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

York Sun Feb. 1, 2017, 4:11 p.m. UTC | #1 
On 01/24/2017 06:42 AM, thomas.graziadei@omicronenergy.com wrote:
> From: Mark Marshall <Mark.Marshall@omicron.at>
>
> We should use the symbolic names for the cache control bits.
>
> Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
> Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com>
> ---

Applied to u-boot-mpc85xx master, awaiting upstream. Thanks.

York
diff mbox

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 932216c..eb817f1 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1373,8 +1373,8 @@  icache_enable:
 	mtlr	r8
 	isync
 	mfspr	r4,L1CSR1
-	ori	r4,r4,0x0001
-	oris	r4,r4,0x0001
+	ori	r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
+	oris	r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
 	mtspr	L1CSR1,r4
 	isync
 	blr
@@ -1402,8 +1402,8 @@  dcache_enable:
 	mtlr	r8
 	isync
 	mfspr	r0,L1CSR0
-	ori	r0,r0,0x0001
-	oris	r0,r0,0x0001
+	ori	r0,r0,(L1CSR0_CPE |  L1CSR0_DCE)@l
+	oris	r0,r0,(L1CSR0_CPE |  L1CSR0_DCE)@h
 	msync
 	isync
 	mtspr	L1CSR0,r0