| Message ID | 1464028337-13426-3-git-send-email-s-anna@ti.com |
|---|---|
| State | Accepted |
| Commit | 27c9596f680ecea01beb52181da72b7d7fab0d8c |
| Delegated to: | Tom Rini |
| Headers | show |
On Tuesday 24 May 2016 12:02 AM, Suman Anna wrote: > Define a set of common macros for the efuse register offsets > (different for each OPP) that are used to get the AVS Class 0 > voltage values and ABB configuration values. Assign these > common macros to the register offsets for OPP_NOM by default > for all voltage domains. These common macros can then be > redefined properly to point to the OPP specific efuse register > offset based on the desired OPP to program a specific voltage > domain. > > Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Thanks and regards, Lokesh > --- > arch/arm/cpu/armv7/omap5/hw_data.c | 20 ++++++++++---------- > arch/arm/include/asm/arch-omap5/clock.h | 7 +++++++ > board/ti/am57xx/board.c | 10 +++++----- > 3 files changed, 22 insertions(+), 15 deletions(-) > > diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c > index 88e8920..948461a 100644 > --- a/arch/arm/cpu/armv7/omap5/hw_data.c > +++ b/arch/arm/cpu/armv7/omap5/hw_data.c > @@ -366,34 +366,34 @@ struct vcores_data omap5430_volts_es2 = { > > struct vcores_data dra752_volts = { > .mpu.value = VDD_MPU_DRA752, > - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, > + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, > .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .mpu.addr = TPS659038_REG_ADDR_SMPS12, > .mpu.pmic = &tps659038, > .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, > > .eve.value = VDD_EVE_DRA752, > - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, > + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, > .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .eve.addr = TPS659038_REG_ADDR_SMPS45, > .eve.pmic = &tps659038, > .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, > > .gpu.value = VDD_GPU_DRA752, > - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, > + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, > .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .gpu.addr = TPS659038_REG_ADDR_SMPS6, > .gpu.pmic = &tps659038, > .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, > > .core.value = VDD_CORE_DRA752, > - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, > + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, > .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .core.addr = TPS659038_REG_ADDR_SMPS7, > .core.pmic = &tps659038, > > .iva.value = VDD_IVA_DRA752, > - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, > + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, > .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .iva.addr = TPS659038_REG_ADDR_SMPS8, > .iva.pmic = &tps659038, > @@ -402,14 +402,14 @@ struct vcores_data dra752_volts = { > > struct vcores_data dra722_volts = { > .mpu.value = VDD_MPU_DRA72x, > - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, > + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, > .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .mpu.addr = TPS65917_REG_ADDR_SMPS1, > .mpu.pmic = &tps659038, > .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, > > .core.value = VDD_CORE_DRA72x, > - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, > + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, > .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .core.addr = TPS65917_REG_ADDR_SMPS2, > .core.pmic = &tps659038, > @@ -419,21 +419,21 @@ struct vcores_data dra722_volts = { > * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. > */ > .gpu.value = VDD_GPU_DRA72x, > - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, > + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, > .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .gpu.addr = TPS65917_REG_ADDR_SMPS3, > .gpu.pmic = &tps659038, > .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, > > .eve.value = VDD_EVE_DRA72x, > - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, > + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, > .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .eve.addr = TPS65917_REG_ADDR_SMPS3, > .eve.pmic = &tps659038, > .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, > > .iva.value = VDD_IVA_DRA72x, > - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, > + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, > .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .iva.addr = TPS65917_REG_ADDR_SMPS3, > .iva.pmic = &tps659038, > diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h > index 9180c67..a850043 100644 > --- a/arch/arm/include/asm/arch-omap5/clock.h > +++ b/arch/arm/include/asm/arch-omap5/clock.h > @@ -283,6 +283,13 @@ > /* STD_FUSE_OPP_VMIN_MPU_4 */ > #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) > > +/* Common Efuse register macros */ > +#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM > +#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM > +#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM > +#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_NOM > +#define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_NOM > + > /* Standard offset is 0.5v expressed in uv */ > #define PALMAS_SMPS_BASE_VOLT_UV 500000 > > diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c > index 86b8f6e..1e978dc 100644 > --- a/board/ti/am57xx/board.c > +++ b/board/ti/am57xx/board.c > @@ -217,34 +217,34 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) > > struct vcores_data beagle_x15_volts = { > .mpu.value = VDD_MPU_DRA752, > - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, > + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, > .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .mpu.addr = TPS659038_REG_ADDR_SMPS12, > .mpu.pmic = &tps659038, > .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, > > .eve.value = VDD_EVE_DRA752, > - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, > + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, > .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .eve.addr = TPS659038_REG_ADDR_SMPS45, > .eve.pmic = &tps659038, > .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, > > .gpu.value = VDD_GPU_DRA752, > - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, > + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, > .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .gpu.addr = TPS659038_REG_ADDR_SMPS45, > .gpu.pmic = &tps659038, > .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, > > .core.value = VDD_CORE_DRA752, > - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, > + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, > .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .core.addr = TPS659038_REG_ADDR_SMPS6, > .core.pmic = &tps659038, > > .iva.value = VDD_IVA_DRA752, > - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, > + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, > .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, > .iva.addr = TPS659038_REG_ADDR_SMPS45, > .iva.pmic = &tps659038, >
On Mon, May 23, 2016 at 01:32:15PM -0500, Anna, Suman wrote: > Define a set of common macros for the efuse register offsets > (different for each OPP) that are used to get the AVS Class 0 > voltage values and ABB configuration values. Assign these > common macros to the register offsets for OPP_NOM by default > for all voltage domains. These common macros can then be > redefined properly to point to the OPP specific efuse register > offset based on the desired OPP to program a specific voltage > domain. > > Signed-off-by: Suman Anna <s-anna@ti.com> > Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 88e8920..948461a 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -366,34 +366,34 @@ struct vcores_data omap5430_volts_es2 = { struct vcores_data dra752_volts = { .mpu.value = VDD_MPU_DRA752, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038, .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, .eve.value = VDD_EVE_DRA752, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, .gpu.value = VDD_GPU_DRA752, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS6, .gpu.pmic = &tps659038, .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, .core.value = VDD_CORE_DRA752, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS659038_REG_ADDR_SMPS7, .core.pmic = &tps659038, .iva.value = VDD_IVA_DRA752, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS8, .iva.pmic = &tps659038, @@ -402,14 +402,14 @@ struct vcores_data dra752_volts = { struct vcores_data dra722_volts = { .mpu.value = VDD_MPU_DRA72x, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS65917_REG_ADDR_SMPS1, .mpu.pmic = &tps659038, .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, .core.value = VDD_CORE_DRA72x, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS65917_REG_ADDR_SMPS2, .core.pmic = &tps659038, @@ -419,21 +419,21 @@ struct vcores_data dra722_volts = { * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. */ .gpu.value = VDD_GPU_DRA72x, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS65917_REG_ADDR_SMPS3, .gpu.pmic = &tps659038, .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, .eve.value = VDD_EVE_DRA72x, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS65917_REG_ADDR_SMPS3, .eve.pmic = &tps659038, .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, .iva.value = VDD_IVA_DRA72x, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS65917_REG_ADDR_SMPS3, .iva.pmic = &tps659038, diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 9180c67..a850043 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -283,6 +283,13 @@ /* STD_FUSE_OPP_VMIN_MPU_4 */ #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) +/* Common Efuse register macros */ +#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM +#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM +#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM +#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_NOM +#define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_NOM + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 86b8f6e..1e978dc 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -217,34 +217,34 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) struct vcores_data beagle_x15_volts = { .mpu.value = VDD_MPU_DRA752, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038, .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, .eve.value = VDD_EVE_DRA752, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, .gpu.value = VDD_GPU_DRA752, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS45, .gpu.pmic = &tps659038, .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, .core.value = VDD_CORE_DRA752, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS659038_REG_ADDR_SMPS6, .core.pmic = &tps659038, .iva.value = VDD_IVA_DRA752, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS45, .iva.pmic = &tps659038,
Define a set of common macros for the efuse register offsets (different for each OPP) that are used to get the AVS Class 0 voltage values and ABB configuration values. Assign these common macros to the register offsets for OPP_NOM by default for all voltage domains. These common macros can then be redefined properly to point to the OPP specific efuse register offset based on the desired OPP to program a specific voltage domain. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm/cpu/armv7/omap5/hw_data.c | 20 ++++++++++---------- arch/arm/include/asm/arch-omap5/clock.h | 7 +++++++ board/ti/am57xx/board.c | 10 +++++----- 3 files changed, 22 insertions(+), 15 deletions(-)