| Message ID | 1463739001-25905-4-git-send-email-yangbo.lu@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | York Sun |
| Headers | show |
On 05/20/2016 03:20 AM, Yangbo Lu wrote: > Erratum Title: > Data timeout error not getting set in case of command with busy > response (R1b) as well as for busy period after last write block > transfer. > > Description: > In the event that a busy timeout occurs for a command with a busy > response (e.g. R1b response) as well as busy period after the last > write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the > IRQSTAT[TC]. Therefore, the current command transfer is never completed. > > Workaround: > Workaround for CMD with busy: > Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and > poll the busy status of the card from the PRSSTAT[DLSL] > > Workaround for busy period after last write block: > 1. After the command completion interrupt (IRQSTAT[CC]), wait for > de-assertion of PRSTAT[WTA]. > 2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll > the busy signal (DAT0) using PRSTAT[DLSL[0]]. > 3. Wait for DAT0 signal to go high (which indicate transfer complete) > or software timer expiry (which indicate data timeout error). > 4. Issue soft reset for data (SYSCTL[RSTD]). > 5. In case of data timeout error (detected in step 3) perform the > error recovery. > > The workaround for CMD with busy has already been applied in eSDHC > driver. This patch is to add workaround for the 2nd issue, and the > fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ > T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). > > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> > --- > arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ > drivers/mmc/fsl_esdhc.c | 26 ++++++++++++++++++++++++++ > include/configs/ls1021aqds.h | 1 + > include/configs/ls1021atwr.h | 1 + > include/configs/ls1043a_common.h | 1 + > include/configs/ls2080a_simu.h | 1 + > include/configs/ls2080aqds.h | 1 + > include/configs/ls2080ardb.h | 1 + > include/fsl_esdhc.h | 1 + > 9 files changed, 41 insertions(+) Yangbo, Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board header file if the erratum applies to the SoC? York
> -----Original Message----- > From: york sun > Sent: Tuesday, July 26, 2016 1:38 AM > To: Yangbo Lu; u-boot@lists.denx.de > Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620 > > On 05/20/2016 03:20 AM, Yangbo Lu wrote: > > Erratum Title: > > Data timeout error not getting set in case of command with busy > > response (R1b) as well as for busy period after last write block > > transfer. > > > > Description: > > In the event that a busy timeout occurs for a command with a busy > > response (e.g. R1b response) as well as busy period after the last > > write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the > > IRQSTAT[TC]. Therefore, the current command transfer is never completed. > > > > Workaround: > > Workaround for CMD with busy: > > Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and > > poll the busy status of the card from the PRSSTAT[DLSL] > > > > Workaround for busy period after last write block: > > 1. After the command completion interrupt (IRQSTAT[CC]), wait for > > de-assertion of PRSTAT[WTA]. > > 2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll > > the busy signal (DAT0) using PRSTAT[DLSL[0]]. > > 3. Wait for DAT0 signal to go high (which indicate transfer complete) > > or software timer expiry (which indicate data timeout error). > > 4. Issue soft reset for data (SYSCTL[RSTD]). > > 5. In case of data timeout error (detected in step 3) perform the > > error recovery. > > > > The workaround for CMD with busy has already been applied in eSDHC > > driver. This patch is to add workaround for the 2nd issue, and the > > fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ > > T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). > > > > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> > > --- > > arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ > > drivers/mmc/fsl_esdhc.c | 26 > ++++++++++++++++++++++++++ > > include/configs/ls1021aqds.h | 1 + > > include/configs/ls1021atwr.h | 1 + > > include/configs/ls1043a_common.h | 1 + > > include/configs/ls2080a_simu.h | 1 + > > include/configs/ls2080aqds.h | 1 + > > include/configs/ls2080ardb.h | 1 + > > include/fsl_esdhc.h | 1 + > > 9 files changed, 41 insertions(+) > > Yangbo, > > Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board > header file if the erratum applies to the SoC? > > York > [Lu Yangbo-B47093] Thanks a lot, York. Could you suggest any better place where I can put this macro? I didn't find such a good place :( Thanks.
On 07/27/2016 04:10 PM, Yangbo Lu wrote: >> -----Original Message----- >> From: york sun >> Sent: Tuesday, July 26, 2016 1:38 AM >> To: Yangbo Lu; u-boot@lists.denx.de >> Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620 >> >> On 05/20/2016 03:20 AM, Yangbo Lu wrote: >>> Erratum Title: >>> Data timeout error not getting set in case of command with busy >>> response (R1b) as well as for busy period after last write block >>> transfer. >>> >>> Description: >>> In the event that a busy timeout occurs for a command with a busy >>> response (e.g. R1b response) as well as busy period after the last >>> write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the >>> IRQSTAT[TC]. Therefore, the current command transfer is never completed. >>> >>> Workaround: >>> Workaround for CMD with busy: >>> Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and >>> poll the busy status of the card from the PRSSTAT[DLSL] >>> >>> Workaround for busy period after last write block: >>> 1. After the command completion interrupt (IRQSTAT[CC]), wait for >>> de-assertion of PRSTAT[WTA]. >>> 2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll >>> the busy signal (DAT0) using PRSTAT[DLSL[0]]. >>> 3. Wait for DAT0 signal to go high (which indicate transfer complete) >>> or software timer expiry (which indicate data timeout error). >>> 4. Issue soft reset for data (SYSCTL[RSTD]). >>> 5. In case of data timeout error (detected in step 3) perform the >>> error recovery. >>> >>> The workaround for CMD with busy has already been applied in eSDHC >>> driver. This patch is to add workaround for the 2nd issue, and the >>> fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ >>> T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). >>> >>> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> >>> --- >>> arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ >>> drivers/mmc/fsl_esdhc.c | 26 >> ++++++++++++++++++++++++++ >>> include/configs/ls1021aqds.h | 1 + >>> include/configs/ls1021atwr.h | 1 + >>> include/configs/ls1043a_common.h | 1 + >>> include/configs/ls2080a_simu.h | 1 + >>> include/configs/ls2080aqds.h | 1 + >>> include/configs/ls2080ardb.h | 1 + >>> include/fsl_esdhc.h | 1 + >>> 9 files changed, 41 insertions(+) >> >> Yangbo, >> >> Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board >> header file if the erratum applies to the SoC? >> >> York >> > [Lu Yangbo-B47093] Thanks a lot, York. > Could you suggest any better place where I can put this macro? > I didn't find such a good place :( If use your patch by default, is there performance degression? I don't know fsl_esdhc controller..so i just ask this. :) > > Thanks. > > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > > >
On 07/27/2016 12:10 AM, Yangbo Lu wrote: >> -----Original Message----- >> From: york sun >> Sent: Tuesday, July 26, 2016 1:38 AM >> To: Yangbo Lu; u-boot@lists.denx.de >> Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620 >> >> On 05/20/2016 03:20 AM, Yangbo Lu wrote: >>> Erratum Title: >>> Data timeout error not getting set in case of command with busy >>> response (R1b) as well as for busy period after last write block >>> transfer. >>> >>> Description: >>> In the event that a busy timeout occurs for a command with a busy >>> response (e.g. R1b response) as well as busy period after the last >>> write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the >>> IRQSTAT[TC]. Therefore, the current command transfer is never completed. >>> >>> Workaround: >>> Workaround for CMD with busy: >>> Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and >>> poll the busy status of the card from the PRSSTAT[DLSL] >>> >>> Workaround for busy period after last write block: >>> 1. After the command completion interrupt (IRQSTAT[CC]), wait for >>> de-assertion of PRSTAT[WTA]. >>> 2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll >>> the busy signal (DAT0) using PRSTAT[DLSL[0]]. >>> 3. Wait for DAT0 signal to go high (which indicate transfer complete) >>> or software timer expiry (which indicate data timeout error). >>> 4. Issue soft reset for data (SYSCTL[RSTD]). >>> 5. In case of data timeout error (detected in step 3) perform the >>> error recovery. >>> >>> The workaround for CMD with busy has already been applied in eSDHC >>> driver. This patch is to add workaround for the 2nd issue, and the >>> fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ >>> T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). >>> >>> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> >>> --- >>> arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ >>> drivers/mmc/fsl_esdhc.c | 26 >> ++++++++++++++++++++++++++ >>> include/configs/ls1021aqds.h | 1 + >>> include/configs/ls1021atwr.h | 1 + >>> include/configs/ls1043a_common.h | 1 + >>> include/configs/ls2080a_simu.h | 1 + >>> include/configs/ls2080aqds.h | 1 + >>> include/configs/ls2080ardb.h | 1 + >>> include/fsl_esdhc.h | 1 + >>> 9 files changed, 41 insertions(+) >> >> Yangbo, >> >> Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board >> header file if the erratum applies to the SoC? >> >> York >> > [Lu Yangbo-B47093] Thanks a lot, York. > Could you suggest any better place where I can put this macro? > I didn't find such a good place :( > arch/arm/include/asm/arch-ls102xa/config.h arch/arm/include/asm/arch-fsl-layerscape/config.h York
Hi Jaehoon, > -----Original Message----- > From: Jaehoon Chung [mailto:jh80.chung@samsung.com] > Sent: Wednesday, July 27, 2016 7:21 PM > To: Yangbo Lu; york sun; u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH 4/4] mmc: add workaround for eSDHC erratum > A009620 > > On 07/27/2016 04:10 PM, Yangbo Lu wrote: > >> -----Original Message----- > >> From: york sun > >> Sent: Tuesday, July 26, 2016 1:38 AM > >> To: Yangbo Lu; u-boot@lists.denx.de > >> Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum > >> A009620 > >> > >> On 05/20/2016 03:20 AM, Yangbo Lu wrote: > >>> Erratum Title: > >>> Data timeout error not getting set in case of command with busy > >>> response (R1b) as well as for busy period after last write block > >>> transfer. > >>> > >>> Description: > >>> In the event that a busy timeout occurs for a command with a busy > >>> response (e.g. R1b response) as well as busy period after the last > >>> write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the > >>> IRQSTAT[TC]. Therefore, the current command transfer is never > completed. > >>> > >>> Workaround: > >>> Workaround for CMD with busy: > >>> Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and > >>> poll the busy status of the card from the PRSSTAT[DLSL] > >>> > >>> Workaround for busy period after last write block: > >>> 1. After the command completion interrupt (IRQSTAT[CC]), wait for > >>> de-assertion of PRSTAT[WTA]. > >>> 2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll > >>> the busy signal (DAT0) using PRSTAT[DLSL[0]]. > >>> 3. Wait for DAT0 signal to go high (which indicate transfer complete) > >>> or software timer expiry (which indicate data timeout error). > >>> 4. Issue soft reset for data (SYSCTL[RSTD]). > >>> 5. In case of data timeout error (detected in step 3) perform the > >>> error recovery. > >>> > >>> The workaround for CMD with busy has already been applied in eSDHC > >>> driver. This patch is to add workaround for the 2nd issue, and the > >>> fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ > >>> T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). > >>> > >>> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> > >>> --- > >>> arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ > >>> drivers/mmc/fsl_esdhc.c | 26 > >> ++++++++++++++++++++++++++ > >>> include/configs/ls1021aqds.h | 1 + > >>> include/configs/ls1021atwr.h | 1 + > >>> include/configs/ls1043a_common.h | 1 + > >>> include/configs/ls2080a_simu.h | 1 + > >>> include/configs/ls2080aqds.h | 1 + > >>> include/configs/ls2080ardb.h | 1 + > >>> include/fsl_esdhc.h | 1 + > >>> 9 files changed, 41 insertions(+) > >> > >> Yangbo, > >> > >> Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in > >> board header file if the erratum applies to the SoC? > >> > >> York > >> > > [Lu Yangbo-B47093] Thanks a lot, York. > > Could you suggest any better place where I can put this macro? > > I didn't find such a good place :( > > If use your patch by default, is there performance degression? > I don't know fsl_esdhc controller..so i just ask this. :) > [Lu Yangbo-B47093] The original code polls 'Transfer Complete' interrupt or 'DMA' interrupt for transfer completion. This patch will change to poll DAT0/BUSY line. There should be no difference, but I think the udelay(100) in polling DAT0/BUSY may have a little affect on performance. Anyway the patch will only apply to the silicon which has this erratum. Thanks. > > > > Thanks. > > > > > > _______________________________________________ > > U-Boot mailing list > > U-Boot@lists.denx.de > > http://lists.denx.de/mailman/listinfo/u-boot > > > > > >
> -----Original Message----- > From: york sun > Sent: Wednesday, July 27, 2016 10:48 PM > To: Yangbo Lu; u-boot@lists.denx.de > Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620 > > On 07/27/2016 12:10 AM, Yangbo Lu wrote: > >> -----Original Message----- > >> From: york sun > >> Sent: Tuesday, July 26, 2016 1:38 AM > >> To: Yangbo Lu; u-boot@lists.denx.de > >> Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum > >> A009620 > >> > >> On 05/20/2016 03:20 AM, Yangbo Lu wrote: > >>> Erratum Title: > >>> Data timeout error not getting set in case of command with busy > >>> response (R1b) as well as for busy period after last write block > >>> transfer. > >>> > >>> Description: > >>> In the event that a busy timeout occurs for a command with a busy > >>> response (e.g. R1b response) as well as busy period after the last > >>> write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the > >>> IRQSTAT[TC]. Therefore, the current command transfer is never > completed. > >>> > >>> Workaround: > >>> Workaround for CMD with busy: > >>> Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and > >>> poll the busy status of the card from the PRSSTAT[DLSL] > >>> > >>> Workaround for busy period after last write block: > >>> 1. After the command completion interrupt (IRQSTAT[CC]), wait for > >>> de-assertion of PRSTAT[WTA]. > >>> 2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll > >>> the busy signal (DAT0) using PRSTAT[DLSL[0]]. > >>> 3. Wait for DAT0 signal to go high (which indicate transfer complete) > >>> or software timer expiry (which indicate data timeout error). > >>> 4. Issue soft reset for data (SYSCTL[RSTD]). > >>> 5. In case of data timeout error (detected in step 3) perform the > >>> error recovery. > >>> > >>> The workaround for CMD with busy has already been applied in eSDHC > >>> driver. This patch is to add workaround for the 2nd issue, and the > >>> fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ > >>> T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). > >>> > >>> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> > >>> --- > >>> arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ > >>> drivers/mmc/fsl_esdhc.c | 26 > >> ++++++++++++++++++++++++++ > >>> include/configs/ls1021aqds.h | 1 + > >>> include/configs/ls1021atwr.h | 1 + > >>> include/configs/ls1043a_common.h | 1 + > >>> include/configs/ls2080a_simu.h | 1 + > >>> include/configs/ls2080aqds.h | 1 + > >>> include/configs/ls2080ardb.h | 1 + > >>> include/fsl_esdhc.h | 1 + > >>> 9 files changed, 41 insertions(+) > >> > >> Yangbo, > >> > >> Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in > >> board header file if the erratum applies to the SoC? > >> > >> York > >> > > [Lu Yangbo-B47093] Thanks a lot, York. > > Could you suggest any better place where I can put this macro? > > I didn't find such a good place :( > > > > arch/arm/include/asm/arch-ls102xa/config.h > arch/arm/include/asm/arch-fsl-layerscape/config.h > > York [Lu Yangbo-B47093] Got it. Thanks a lot, York :) I will send the new version.
Hi Yangbo, On 07/28/2016 12:20 PM, Yangbo Lu wrote: > Hi Jaehoon, > > >> -----Original Message----- >> From: Jaehoon Chung [mailto:jh80.chung@samsung.com] >> Sent: Wednesday, July 27, 2016 7:21 PM >> To: Yangbo Lu; york sun; u-boot@lists.denx.de >> Subject: Re: [U-Boot] [PATCH 4/4] mmc: add workaround for eSDHC erratum >> A009620 >> >> On 07/27/2016 04:10 PM, Yangbo Lu wrote: >>>> -----Original Message----- >>>> From: york sun >>>> Sent: Tuesday, July 26, 2016 1:38 AM >>>> To: Yangbo Lu; u-boot@lists.denx.de >>>> Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum >>>> A009620 >>>> >>>> On 05/20/2016 03:20 AM, Yangbo Lu wrote: >>>>> Erratum Title: >>>>> Data timeout error not getting set in case of command with busy >>>>> response (R1b) as well as for busy period after last write block >>>>> transfer. >>>>> >>>>> Description: >>>>> In the event that a busy timeout occurs for a command with a busy >>>>> response (e.g. R1b response) as well as busy period after the last >>>>> write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the >>>>> IRQSTAT[TC]. Therefore, the current command transfer is never >> completed. >>>>> >>>>> Workaround: >>>>> Workaround for CMD with busy: >>>>> Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and >>>>> poll the busy status of the card from the PRSSTAT[DLSL] >>>>> >>>>> Workaround for busy period after last write block: >>>>> 1. After the command completion interrupt (IRQSTAT[CC]), wait for >>>>> de-assertion of PRSTAT[WTA]. >>>>> 2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll >>>>> the busy signal (DAT0) using PRSTAT[DLSL[0]]. >>>>> 3. Wait for DAT0 signal to go high (which indicate transfer complete) >>>>> or software timer expiry (which indicate data timeout error). >>>>> 4. Issue soft reset for data (SYSCTL[RSTD]). >>>>> 5. In case of data timeout error (detected in step 3) perform the >>>>> error recovery. >>>>> >>>>> The workaround for CMD with busy has already been applied in eSDHC >>>>> driver. This patch is to add workaround for the 2nd issue, and the >>>>> fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ >>>>> T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). >>>>> >>>>> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> >>>>> --- >>>>> arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ >>>>> drivers/mmc/fsl_esdhc.c | 26 >>>> ++++++++++++++++++++++++++ >>>>> include/configs/ls1021aqds.h | 1 + >>>>> include/configs/ls1021atwr.h | 1 + >>>>> include/configs/ls1043a_common.h | 1 + >>>>> include/configs/ls2080a_simu.h | 1 + >>>>> include/configs/ls2080aqds.h | 1 + >>>>> include/configs/ls2080ardb.h | 1 + >>>>> include/fsl_esdhc.h | 1 + >>>>> 9 files changed, 41 insertions(+) >>>> >>>> Yangbo, >>>> >>>> Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in >>>> board header file if the erratum applies to the SoC? >>>> >>>> York >>>> >>> [Lu Yangbo-B47093] Thanks a lot, York. >>> Could you suggest any better place where I can put this macro? >>> I didn't find such a good place :( >> >> If use your patch by default, is there performance degression? >> I don't know fsl_esdhc controller..so i just ask this. :) >> > > [Lu Yangbo-B47093] The original code polls 'Transfer Complete' interrupt or 'DMA' interrupt for transfer completion. > This patch will change to poll DAT0/BUSY line. > There should be no difference, but I think the udelay(100) in polling DAT0/BUSY may have a little affect on performance. > Anyway the patch will only apply to the silicon which has this erratum. Thanks for explanation! :) I think you can split to config files and mmc side. And while (esdhc_read32(®s->prsstat) & PRSSTAT_WTA); This code has the potential infinite loop.. while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)); Ditto. In my experience, it's good that potential infinite loop case is removed. Because we can't sure that this condition has to hit. :) Best Regards, Jaehoon Chung > > Thanks. > >>> >>> Thanks. >>> >>> >>> _______________________________________________ >>> U-Boot mailing list >>> U-Boot@lists.denx.de >>> http://lists.denx.de/mailman/listinfo/u-boot >>> >>> >>> > > > >
Hi Jaehoon, > -----Original Message----- > From: Jaehoon Chung [mailto:jh80.chung@samsung.com] > Sent: Thursday, July 28, 2016 1:01 PM > To: Yangbo Lu; york sun; u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH 4/4] mmc: add workaround for eSDHC erratum > A009620 > > Hi Yangbo, > > On 07/28/2016 12:20 PM, Yangbo Lu wrote: > > Hi Jaehoon, > > > > > >> -----Original Message----- > >> From: Jaehoon Chung [mailto:jh80.chung@samsung.com] > >> Sent: Wednesday, July 27, 2016 7:21 PM > >> To: Yangbo Lu; york sun; u-boot@lists.denx.de > >> Subject: Re: [U-Boot] [PATCH 4/4] mmc: add workaround for eSDHC > >> erratum > >> A009620 > >> > >> On 07/27/2016 04:10 PM, Yangbo Lu wrote: > >>>> -----Original Message----- > >>>> From: york sun > >>>> Sent: Tuesday, July 26, 2016 1:38 AM > >>>> To: Yangbo Lu; u-boot@lists.denx.de > >>>> Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum > >>>> A009620 > >>>> > >>>> On 05/20/2016 03:20 AM, Yangbo Lu wrote: > >>>>> Erratum Title: > >>>>> Data timeout error not getting set in case of command with busy > >>>>> response (R1b) as well as for busy period after last write block > >>>>> transfer. > >>>>> > >>>>> Description: > >>>>> In the event that a busy timeout occurs for a command with a busy > >>>>> response (e.g. R1b response) as well as busy period after the last > >>>>> write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the > >>>>> IRQSTAT[TC]. Therefore, the current command transfer is never > >> completed. > >>>>> > >>>>> Workaround: > >>>>> Workaround for CMD with busy: > >>>>> Don't set the XFRTYP[RSP]=2'b11 for commands with busy response > >>>>> and poll the busy status of the card from the PRSSTAT[DLSL] > >>>>> > >>>>> Workaround for busy period after last write block: > >>>>> 1. After the command completion interrupt (IRQSTAT[CC]), wait for > >>>>> de-assertion of PRSTAT[WTA]. > >>>>> 2. Once PRSTAT[WTA] is de-asserted, start the software timer and > poll > >>>>> the busy signal (DAT0) using PRSTAT[DLSL[0]]. > >>>>> 3. Wait for DAT0 signal to go high (which indicate transfer > complete) > >>>>> or software timer expiry (which indicate data timeout error). > >>>>> 4. Issue soft reset for data (SYSCTL[RSTD]). > >>>>> 5. In case of data timeout error (detected in step 3) perform the > >>>>> error recovery. > >>>>> > >>>>> The workaround for CMD with busy has already been applied in eSDHC > >>>>> driver. This patch is to add workaround for the 2nd issue, and the > >>>>> fixup platforms include > >>>>> PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ > >>>>> T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). > >>>>> > >>>>> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> > >>>>> --- > >>>>> arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ > >>>>> drivers/mmc/fsl_esdhc.c | 26 > >>>> ++++++++++++++++++++++++++ > >>>>> include/configs/ls1021aqds.h | 1 + > >>>>> include/configs/ls1021atwr.h | 1 + > >>>>> include/configs/ls1043a_common.h | 1 + > >>>>> include/configs/ls2080a_simu.h | 1 + > >>>>> include/configs/ls2080aqds.h | 1 + > >>>>> include/configs/ls2080ardb.h | 1 + > >>>>> include/fsl_esdhc.h | 1 + > >>>>> 9 files changed, 41 insertions(+) > >>>> > >>>> Yangbo, > >>>> > >>>> Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in > >>>> board header file if the erratum applies to the SoC? > >>>> > >>>> York > >>>> > >>> [Lu Yangbo-B47093] Thanks a lot, York. > >>> Could you suggest any better place where I can put this macro? > >>> I didn't find such a good place :( > >> > >> If use your patch by default, is there performance degression? > >> I don't know fsl_esdhc controller..so i just ask this. :) > >> > > > > [Lu Yangbo-B47093] The original code polls 'Transfer Complete' > interrupt or 'DMA' interrupt for transfer completion. > > This patch will change to poll DAT0/BUSY line. > > There should be no difference, but I think the udelay(100) in polling > DAT0/BUSY may have a little affect on performance. > > Anyway the patch will only apply to the silicon which has this erratum. > > Thanks for explanation! :) > I think you can split to config files and mmc side. [Lu Yangbo-B47093] Ok, this should be no problem :) > > And > > while (esdhc_read32(®s->prsstat) & PRSSTAT_WTA); > > This code has the potential infinite loop.. > > while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)); > > Ditto. In my experience, it's good that potential infinite loop case is > removed. > Because we can't sure that this condition has to hit. :) > [Lu Yangbo-B47093] I think you're right. Although this would be ok from hardware perspective, there is still potential risk. But how to remove them, is there any good idea? Is it proper to add timeout checking here ? Thanks. > Best Regards, > Jaehoon Chung > > > > > Thanks. > > > >>> > >>> Thanks. > >>> > >>> > >>> _______________________________________________ > >>> U-Boot mailing list > >>> U-Boot@lists.denx.de > >>> http://lists.denx.de/mailman/listinfo/u-boot > >>> > >>> > >>> > > > > > > > >
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index eccc146..197ee42 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -148,6 +148,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 @@ -369,6 +370,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -530,6 +532,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 @@ -568,6 +571,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 @@ -686,6 +690,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007798 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X @@ -802,6 +807,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -823,6 +829,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #endif #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) #define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_MAX_CPUS 1 #endif @@ -882,6 +889,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #elif defined(CONFIG_PPC_T2081) #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 744037e..fba87d2 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -470,6 +470,32 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_pio_read_write(mmc, data); #else +#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 + int timeout = 5000; + if (data->flags & MMC_DATA_WRITE) { + while (esdhc_read32(®s->prsstat) & PRSSTAT_WTA) + ; + + /* Poll on DATA0 line for 500 ms */ + while (!(esdhc_read32(®s->prsstat) & PRSSTAT_DAT0)) { + udelay(100); + timeout--; + if (timeout <= 0) { + err = TIMEOUT; + break; + } + } + if (!err) { + esdhc_write32(®s->sysctl, + esdhc_read32(®s->sysctl) | + SYSCTL_RSTD); + while ((esdhc_read32(®s->sysctl) & + SYSCTL_RSTD)) + ; + } + goto out; + } +#endif do { irqstat = esdhc_read32(®s->irqstat); diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 62cf6e5..a656976 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -415,6 +415,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_GENERIC_MMC #define CONFIG_CMD_FAT diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b2e431a..912af90 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -303,6 +303,7 @@ #define CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_GENERIC_MMC #define CONFIG_CMD_FAT diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e900c50..e1e1518 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -186,6 +186,7 @@ #define CONFIG_CMD_MMC #define CONFIG_CMD_FAT #define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #define CONFIG_GENERIC_MMC #define CONFIG_DOS_PARTITION diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index 0dbe95f..a431b66 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -134,6 +134,7 @@ #ifdef CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #define CONFIG_GENERIC_MMC #define CONFIG_CMD_FAT diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 91fad0a..5c38bdf 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -328,6 +328,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #define CONFIG_GENERIC_MMC #define CONFIG_CMD_FAT diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 15a1172..518aa17 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -310,6 +310,7 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #define CONFIG_GENERIC_MMC #define CONFIG_CMD_FAT diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index fa760a5..2d049b7 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -91,6 +91,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_WTA (0x00000100) #define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002)
Erratum Title: Data timeout error not getting set in case of command with busy response (R1b) as well as for busy period after last write block transfer. Description: In the event that a busy timeout occurs for a command with a busy response (e.g. R1b response) as well as busy period after the last write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the IRQSTAT[TC]. Therefore, the current command transfer is never completed. Workaround: Workaround for CMD with busy: Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and poll the busy status of the card from the PRSSTAT[DLSL] Workaround for busy period after last write block: 1. After the command completion interrupt (IRQSTAT[CC]), wait for de-assertion of PRSTAT[WTA]. 2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll the busy signal (DAT0) using PRSTAT[DLSL[0]]. 3. Wait for DAT0 signal to go high (which indicate transfer complete) or software timer expiry (which indicate data timeout error). 4. Issue soft reset for data (SYSCTL[RSTD]). 5. In case of data timeout error (detected in step 3) perform the error recovery. The workaround for CMD with busy has already been applied in eSDHC driver. This patch is to add workaround for the 2nd issue, and the fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A). Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> --- arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ drivers/mmc/fsl_esdhc.c | 26 ++++++++++++++++++++++++++ include/configs/ls1021aqds.h | 1 + include/configs/ls1021atwr.h | 1 + include/configs/ls1043a_common.h | 1 + include/configs/ls2080a_simu.h | 1 + include/configs/ls2080aqds.h | 1 + include/configs/ls2080ardb.h | 1 + include/fsl_esdhc.h | 1 + 9 files changed, 41 insertions(+)