Message ID | 1460717877-24262-1-git-send-email-hs@denx.de |
---|---|
State | Deferred |
Delegated to: | Tom Rini |
Headers | show |
Hi Heiko, On Fri, Apr 15, 2016 at 6:57 PM, Heiko Schocher <hs@denx.de> wrote: > Fix following DTC warnings for all x86 boards. > > There was a warning like: > Warning (unit_address_vs_reg): Node /microcode/update@0 has a unit name, but no reg property > Warning (unit_address_vs_reg): Node /microcode/update@1 has a unit name, but no reg property > > I replaced "udpate@" with "update_". Please test > this patch > > Signed-off-by: Heiko Schocher <hs@denx.de> > --- > This warnings pop up with the DTC compiler: > $ /tmp/dtc/dtc -v > Version: DTC 1.4.1-gbeef80b8 > > This fixes the compile warnings for: > https://travis-ci.org/u-boot/u-boot/jobs/122880432 > > see: > https://travis-ci.org/hsdenx/u-boot/jobs/123281030 > > Tested with sandbox, following steps work as before: > > make sandbox_defconfig > make > ./u-boot -d u-boot.dtb > > but "ut all" drops warnings ... but this patch introduced > no new warnings ... > > output of test/py : > (deleted the long lines) > > +make O=/home/hs/zug/travis/u-boot.git/build-sandbox -s sandbox_defconfig > +make O=/home/hs/zug/travis/u-boot.git/build-sandbox -s -j8 > platform linux2 -- Python 2.7.10, pytest-2.8.7, py-1.4.31, pluggy-0.3.1 > rootdir: /home/hs/zug/travis/u-boot.git, inifile: > collected 204 items > > test/py/tests/test_000_version.py . > test/py/tests/test_dfu.py s > test/py/tests/test_env.py ........ > test/py/tests/test_help.py . > test/py/tests/test_hush_if_test.py ....................................................... > test/py/tests/test_md.py .. > test/py/tests/test_net.py .ssss > test/py/tests/test_sandbox_exit.py .. > test/py/tests/test_shell_basics.py .... > test/py/tests/test_sleep.py . > test/py/tests/test_ums.py s > test/py/tests/test_unknown_cmd.py . > test/py/tests/test_ut.py ......................................................................................F................................... > > u_boot_console = <u_boot_console_sandbox.ConsoleSandbox object at 0x7f68ce2852d0>, ut_subtest = 'dm spi_flash' > > def test_ut(u_boot_console, ut_subtest): > """Execute a "ut" subtest.""" > > output = u_boot_console.run_command('ut ' + ut_subtest) >> assert output.endswith('Failures: 0') > E assert <built-in method endswith of str object at 0x7f68cf10e6d0>('Failures: 0') > E + where <built-in method endswith of str object at 0x7f68cf10e6d0> = 'Test: dm_test_spi_flash\r\r\n2097152 bytes written in 24 ms (83.3 MiB/s)\r\r\nSF: Detected M25P16 with page size 256 ...d_list( "sb save hostfs - 0 spi.bin 200000;" "sf probe;" "sf test 0 10000", -1, 0): Expected 0, got 1\r\r\nFailures: 1'.endswith > > test/py/tests/test_ut.py:29: AssertionError > > => ut dm spi_flash > Test: dm_test_spi_flash > 2097152 bytes written in 24 ms (83.3 MiB/s) > SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB > SPI flash test: > SF: Timeout! > Erase failed > Test failed > ../test/dm/sf.c:34, dm_test_spi_flash(): 0 == run_command_list( "sb save hostfs - 0 spi.bin 200000;" "sf probe;" "sf test 0 10000", -1, 0): Expected 0, got 1 > Failures: 1 > => > > This error is also without this patch ... may I find > time to fix it too... > > > arch/sandbox/dts/sandbox.dts | 30 ++++++++-------- > arch/sandbox/dts/test.dts | 58 +++++++++++++++---------------- > arch/x86/dts/bayleybay.dts | 22 ++++++------ > arch/x86/dts/broadwell_som-6896.dts | 2 +- > arch/x86/dts/chromebook_link.dts | 22 ++++++------ > arch/x86/dts/chromebook_samus.dts | 30 ++++++++-------- > arch/x86/dts/chromebox_panther.dts | 12 +++---- > arch/x86/dts/conga-qeval20-qa3-e3845.dts | 20 +++++------ > arch/x86/dts/cougarcanyon2.dts | 18 +++++----- > arch/x86/dts/crownbay.dts | 8 ++--- > arch/x86/dts/galileo.dts | 8 ++--- > arch/x86/dts/minnowmax.dts | 30 ++++++++-------- > arch/x86/dts/qemu-x86_i440fx.dts | 2 +- > arch/x86/dts/qemu-x86_q35.dts | 2 +- > arch/x86/dts/rtc.dtsi | 2 +- > arch/x86/dts/serial.dtsi | 2 +- > arch/x86/dts/skeleton.dtsi | 2 +- > doc/device-tree-bindings/pmic/sandbox.txt | 2 +- > drivers/misc/cros_ec.c | 6 ++-- > include/sandbox-adc.h | 2 +- > test/dm/bus.c | 4 +-- > test/dm/eth.c | 4 +-- > test/dm/gpio.c | 2 +- > test/dm/pmic.c | 4 +-- > test/dm/spmi.c | 2 +- > test/dm/test-fdt.c | 16 ++++----- > 26 files changed, 156 insertions(+), 156 deletions(-) > > diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts > index 2ae4014..796de3a 100644 > --- a/arch/sandbox/dts/sandbox.dts > +++ b/arch/sandbox/dts/sandbox.dts > @@ -34,13 +34,13 @@ > #size-cells = <1>; > > /* Information for sandbox */ > - ro { > + ro@0 { > reg = <0 0xf000>; > }; > - wp-ro { > + wp-ro@f000 { > reg = <0xf000 0x1000>; > }; > - rw { > + rw@10000 { > reg = <0x10000 0x10000>; > }; > }; > @@ -64,7 +64,7 @@ > host-raw-interface = "lo"; > }; > > - gpio_a: gpios@0 { > + gpio_a: gpios_0 { > gpio-controller; > compatible = "sandbox,gpio"; > #gpio-cells = <1>; > @@ -72,7 +72,7 @@ > num-gpios = <20>; > }; > > - gpio_b: gpios@1 { > + gpio_b: gpios_1 { > gpio-controller; > compatible = "sandbox,gpio"; > #gpio-cells = <2>; > @@ -111,7 +111,7 @@ > compatible = "sandbox,i2c-rtc"; > }; > }; > - sandbox_pmic: sandbox_pmic { > + sandbox_pmic: sandbox_pmic@40 { > reg = <0x40>; > }; > }; > @@ -123,7 +123,7 @@ > yres = <768>; > }; > > - pci: pci-controller { > + pci: pci-controller@0 { > compatible = "sandbox,pci"; > device_type = "pci"; > #address-cells = <3>; > @@ -133,7 +133,7 @@ > pci@1f,0 { > compatible = "pci-generic"; > reg = <0xf800 0 0 0 0>; > - emul@1f,0 { > + emul_1f,0 { > compatible = "sandbox,swap-case"; > }; > }; > @@ -154,7 +154,7 @@ > }; > }; > > - reset@1 { > + reset { > compatible = "sandbox,reset"; > }; > > @@ -203,21 +203,21 @@ > pinctrl-0 = <&pinctrl_serial0>; > }; > > - usb@0 { > + usb0 { > compatible = "sandbox,usb"; > status = "disabled"; > hub { > compatible = "sandbox,usb-hub"; > #address-cells = <1>; > #size-cells = <0>; > - flash-stick { > + flash-stick@0 { > reg = <0>; > compatible = "sandbox,usb-flash"; > }; > }; > }; > > - usb@1 { > + usb1 { > compatible = "sandbox,usb"; > hub { > compatible = "usb-hub"; > @@ -226,7 +226,7 @@ > compatible = "sandbox,usb-hub"; > #address-cells = <1>; > #size-cells = <0>; > - flash-stick { > + flash-stick@0 { > reg = <0>; > compatible = "sandbox,usb-flash"; > sandbox,filepath = "flash.bin"; > @@ -235,12 +235,12 @@ > }; > }; > > - usb@2 { > + usb2 { > compatible = "sandbox,usb"; > status = "disabled"; > }; > > - spmi: spmi@0 { > + spmi: spmi0 { > compatible = "sandbox,spmi"; > #address-cells = <0x1>; > #size-cells = <0x1>; > diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts > index 8930009..9c4e6e2 100644 > --- a/arch/sandbox/dts/test.dts > +++ b/arch/sandbox/dts/test.dts > @@ -18,19 +18,19 @@ > rtc0 = &rtc_0; > rtc1 = &rtc_1; > spi0 = "/spi@0"; > - testfdt6 = "/e-test"; > - testbus3 = "/some-bus"; > - testfdt0 = "/some-bus/c-test@0"; > - testfdt1 = "/some-bus/c-test@1"; > - testfdt3 = "/b-test"; > - testfdt5 = "/some-bus/c-test@5"; > - testfdt8 = "/a-test"; > + testfdt6 = "/e-test@3"; > + testbus3 = "/some-bus@3"; > + testfdt0 = "/some-bus@3/c-test@0"; > + testfdt1 = "/some-bus@3/c-test@1"; > + testfdt3 = "/b-test@3"; > + testfdt5 = "/some-bus@3/c-test@5"; > + testfdt8 = "/a-test@0"; > usb0 = &usb_0; > usb1 = &usb_1; > usb2 = &usb_2; > }; > > - a-test { > + a-test@0 { > reg = <0 1>; > compatible = "denx,u-boot-fdt-test"; > ping-expect = <0>; > @@ -43,23 +43,23 @@ > <&gpio_b 9 0xc 3 2 1>; > }; > > - junk { > + junk@1 { > reg = <1 1>; > compatible = "not,compatible"; > }; > > - no-compatible { > + no-compatible@2 { > reg = <2 1>; > }; > > - b-test { > + b-test@3 { > reg = <3 1>; > compatible = "denx,u-boot-fdt-test"; > ping-expect = <3>; > ping-add = <3>; > }; > > - some-bus { > + some-bus@3 { > #address-cells = <1>; > #size-cells = <0>; > compatible = "denx,u-boot-test-bus"; > @@ -86,14 +86,14 @@ > }; > }; > > - d-test { > + d-test@3 { > reg = <3 1>; > ping-expect = <6>; > ping-add = <6>; > compatible = "google,another-fdt-test"; > }; > > - e-test { > + e-test@3 { > reg = <3 1>; > ping-expect = <6>; > ping-add = <6>; > @@ -108,7 +108,7 @@ > compatible = "denx,u-boot-fdt-test"; > }; > > - clk@0 { > + clk { > compatible = "sandbox,clk"; > }; > > @@ -124,7 +124,7 @@ > fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>; > }; > > - eth_3: sbe5 { > + eth_3: sbe5@10005000 { > compatible = "sandbox,eth"; > reg = <0x10005000 0x1000>; > fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x33>; > @@ -184,12 +184,12 @@ > }; > }; > > - sandbox_pmic: sandbox_pmic { > + sandbox_pmic: sandbox_pmic@40 { > reg = <0x40>; > }; > }; > > - adc@0 { > + adc { > compatible = "sandbox,adc"; > vdd-supply = <&buck2>; > vss-microvolts = <0>; > @@ -220,7 +220,7 @@ > compatible = "sandbox,mmc"; > }; > > - pci: pci-controller { > + pci: pci-controller@0 { > compatible = "sandbox,pci"; > device_type = "pci"; > #address-cells = <3>; > @@ -230,7 +230,7 @@ > pci@1f,0 { > compatible = "pci-generic"; > reg = <0xf800 0 0 0 0>; > - emul@1f,0 { > + emul_1f,0 { > compatible = "sandbox,swap-case"; > }; > }; > @@ -240,20 +240,20 @@ > compatible = "sandbox,ram"; > }; > > - reset@0 { > + reset0 { > compatible = "sandbox,warm-reset"; > }; > > - reset@1 { > + reset1 { > compatible = "sandbox,reset"; > }; > > - rproc_1: rproc@1 { > + rproc_1: rproc1 { > compatible = "sandbox,test-processor"; > remoteproc-name = "remoteproc-test-dev1"; > }; > > - rproc_2: rproc@2 { > + rproc_2: rproc2 { > compatible = "sandbox,test-processor"; > internal-memory-mapped; > remoteproc-name = "remoteproc-test-dev2"; > @@ -296,21 +296,21 @@ > u-boot,dm-pre-reloc; > }; > > - usb_0: usb@0 { > + usb_0: usb0 { > compatible = "sandbox,usb"; > status = "disabled"; > hub { > compatible = "sandbox,usb-hub"; > #address-cells = <1>; > #size-cells = <0>; > - flash-stick { > + flash-stick@0 { > reg = <0>; > compatible = "sandbox,usb-flash"; > }; > }; > }; > > - usb_1: usb@1 { > + usb_1: usb1 { > compatible = "sandbox,usb"; > hub { > compatible = "usb-hub"; > @@ -346,12 +346,12 @@ > }; > }; > > - usb_2: usb@2 { > + usb_2: usb2 { > compatible = "sandbox,usb"; > status = "disabled"; > }; > > - spmi: spmi@0 { > + spmi: spmi0 { > compatible = "sandbox,spmi"; > #address-cells = <0x1>; > #size-cells = <0x1>; > diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts > index 4ea9262..207e7e0 100644 > --- a/arch/x86/dts/bayleybay.dts > +++ b/arch/x86/dts/bayleybay.dts > @@ -65,7 +65,7 @@ > }; > }; > > - pci { > + pci@0 { > compatible = "pci-x86"; > #address-cells = <3>; > #size-cells = <2>; > @@ -155,49 +155,49 @@ > compatible = "winbond,w25q64dw", > "spi-flash"; > memory-map = <0xff800000 0x00800000>; > - rw-mrc-cache { > + rw-mrc-cache@6e0000 { > label = "rw-mrc-cache"; > reg = <0x006e0000 0x00010000>; > }; > }; > }; > > - gpioa { > + gpioa@0 { What about just gpio@0? > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0 0x20>; > bank-name = "A"; > }; > > - gpiob { > + gpiob@20 { and gpio@20? > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x20 0x20>; > bank-name = "B"; > }; > > - gpioc { > + gpioc@40 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x40 0x20>; > bank-name = "C"; > }; > > - gpiod { > + gpiod@60 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x60 0x20>; > bank-name = "D"; > }; > > - gpioe { > + gpioe@80 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x80 0x20>; > bank-name = "E"; > }; > > - gpiof { > + gpiof@a0 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0xA0 0x20>; > @@ -245,13 +245,13 @@ > }; > > microcode { > - update@0 { > + update_0 { update0? > #include "microcode/m0230671117.dtsi" > }; > - update@1 { > + update_1 { > #include "microcode/m0130673322.dtsi" > }; > - update@2 { > + update_2 { > #include "microcode/m0130679901.dtsi" > }; > }; > diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts > index 4bb0a34..674d09a 100644 > --- a/arch/x86/dts/broadwell_som-6896.dts > +++ b/arch/x86/dts/broadwell_som-6896.dts > @@ -21,7 +21,7 @@ > stdout-path = "/serial"; > }; > > - pci { > + pci@0 { > compatible = "pci-x86"; > #address-cells = <3>; > #size-cells = <2>; > diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts > index fb1b31d..41aae38 100644 > --- a/arch/x86/dts/chromebook_link.dts > +++ b/arch/x86/dts/chromebook_link.dts > @@ -64,7 +64,7 @@ > intel,duplicate-por; > }; > > - pch_pinctrl { > + pch_pinctrl@0 { > compatible = "intel,x86-pinctrl"; > u-boot,dm-pre-reloc; > reg = <0 0>; > @@ -217,7 +217,7 @@ > > }; > > - pci { > + pci@0 { > compatible = "pci-x86"; > #address-cells = <3>; > #size-cells = <2>; > @@ -235,7 +235,7 @@ > spd { > #address-cells = <1>; > #size-cells = <0>; > - elpida_4Gb_1600_x16 { > + elpida_4Gb_1600_x16@0 { > reg = <0>; > data = [92 10 0b 03 04 19 02 02 > 03 52 01 08 0a 00 fe 00 > @@ -270,7 +270,7 @@ > 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00]; > }; > - samsung_4Gb_1600_1.35v_x16 { > + samsung_4Gb_1600_1.35v_x16@1 { > reg = <1>; > data = [92 11 0b 03 04 19 02 02 > 03 11 01 08 0a 00 fe 00 > @@ -305,7 +305,7 @@ > 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00]; > }; > - micron_4Gb_1600_1.35v_x16 { > + micron_4Gb_1600_1.35v_x16@2 { > reg = <2>; > data = [92 11 0b 03 04 19 02 02 > 03 11 01 08 0a 00 fe 00 > @@ -397,14 +397,14 @@ > compatible = "winbond,w25q64", > "spi-flash"; > memory-map = <0xff800000 0x00800000>; > - rw-mrc-cache { > + rw-mrc-cache@3e0000 { > label = "rw-mrc-cache"; > reg = <0x003e0000 0x00010000>; > }; > }; > }; > > - gpio_a: gpioa { > + gpio_a: gpioa@0 { ditto > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > #gpio-cells = <2>; > @@ -413,7 +413,7 @@ > bank-name = "A"; > }; > > - gpio_b: gpiob { > + gpio_b: gpiob@30 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > #gpio-cells = <2>; > @@ -422,7 +422,7 @@ > bank-name = "B"; > }; > > - gpio_c: gpioc { > + gpio_c: gpioc@40 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > #gpio-cells = <2>; > @@ -471,13 +471,13 @@ > }; > }; > > - tpm { > + tpm@fed40000 { > reg = <0xfed40000 0x5000>; > compatible = "infineon,slb9635lpc"; > }; > > microcode { > - update@0 { > + update_1 { This should be update0. > #include "microcode/m12306a9_0000001b.dtsi" > }; > }; > diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts > index 5dd3e57..103e26f 100644 > --- a/arch/x86/dts/chromebook_samus.dts > +++ b/arch/x86/dts/chromebook_samus.dts > @@ -65,7 +65,7 @@ > intel,duplicate-por; > }; > > - pch_pinctrl { > + pch_pinctrl@0 { > compatible = "intel,x86-broadwell-pinctrl"; > u-boot,dm-pre-reloc; > reg = <0 0>; > @@ -131,7 +131,7 @@ > pirq-apic = <PIRQ_APIC_ROUTE>; > }; > > - soc_gpio@0 { > + soc_gpio { > config = > <0 &gpio_unused 0>, /* unused */ > <1 &gpio_unused 0>, /* unused */ > @@ -231,7 +231,7 @@ > }; > }; > > - pci { > + pci@0 { > compatible = "pci-x86"; > #address-cells = <3>; > #size-cells = <2>; > @@ -249,7 +249,7 @@ > spd { > #address-cells = <1>; > #size-cells = <0>; > - samsung_4 { > + samsung_4@6 { > reg = <6>; > data = [91 20 f1 03 04 11 05 0b > 03 11 01 08 0a 00 50 01 > @@ -284,7 +284,7 @@ > 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00]; > }; > - hynix-h9ccnnnbltmlar-ntm-lpddr3-32 { > + hynix-h9ccnnnbltmlar-ntm-lpddr3-32@8 { > /* > * banks 8, ranks 2, rows 14, > * columns 10, density 4096 mb, x32 > @@ -323,7 +323,7 @@ > 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00]; > }; > - samsung_8 { > + samsung_8@10 { > reg = <10>; > data = [91 20 f1 03 04 12 05 0a > 03 11 01 08 0a 00 50 01 > @@ -358,7 +358,7 @@ > 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00]; > }; > - hynix-h9ccnnnbltmlar-ntm-lpddr3-16 { > + hynix-h9ccnnnbltmlar-ntm-lpddr3-16@12 { > /* > * banks 8, ranks 2, rows 14, > * columns 11, density 4096 mb, x16 > @@ -397,7 +397,7 @@ > 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00]; > }; > - hynix-h9ccnnncltmlar-lpddr3 { > + hynix-h9ccnnncltmlar-lpddr3@13 { > /* > * banks 8, ranks 2, rows 15, > * columns 11, density 8192 mb, x16 > @@ -436,7 +436,7 @@ > 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00]; > }; > - elpida-edfb232a1ma { > + elpida-edfb232a1ma@15 { > /* > * banks 8, ranks 2, rows 15, > * columns 11, density 8192 mb, x16 > @@ -539,14 +539,14 @@ > compatible = "winbond,w25q64", > "spi-flash"; > memory-map = <0xff800000 0x00800000>; > - rw-mrc-cache { > + rw-mrc-cache@3e0000 { > label = "rw-mrc-cache"; > reg = <0x003e0000 0x00010000>; > }; > }; > }; > > - gpio_a: gpioa { > + gpio_a: gpioa@0 { > compatible = "intel,broadwell-gpio"; > u-boot,dm-pre-reloc; > #gpio-cells = <2>; > @@ -555,7 +555,7 @@ > bank-name = "A"; > }; > > - gpio_b: gpiob { > + gpio_b: gpiob@1 { > compatible = "intel,broadwell-gpio"; > u-boot,dm-pre-reloc; > #gpio-cells = <2>; > @@ -564,7 +564,7 @@ > bank-name = "B"; > }; > > - gpio_c: gpioc { > + gpio_c: gpioc@2 { > compatible = "intel,broadwell-gpio"; > u-boot,dm-pre-reloc; > #gpio-cells = <2>; > @@ -614,13 +614,13 @@ > }; > }; > > - tpm { > + tpm@fed40000 { > reg = <0xfed40000 0x5000>; > compatible = "infineon,slb9635lpc"; > }; > > microcode { > - update@0 { > + update_1 { This should be update0. > #include "microcode/mc0306d4_00000018.dtsi" > }; > }; > diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts > index 480b366..4f88778 100644 > --- a/arch/x86/dts/chromebox_panther.dts > +++ b/arch/x86/dts/chromebox_panther.dts > @@ -22,7 +22,7 @@ > stdout-path = "/serial"; > }; > > - pci { > + pci@0 { > compatible = "pci-x86"; > #address-cells = <3>; > #size-cells = <2>; > @@ -48,28 +48,28 @@ > compatible = "winbond,w25q64", > "spi-flash"; > memory-map = <0xff800000 0x00800000>; > - rw-mrc-cache { > + rw-mrc-cache@3e0000 { > label = "rw-mrc-cache"; > reg = <0x003e0000 0x00010000>; > }; > }; > }; > > - gpioa { > + gpioa@0 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0 0x10>; > bank-name = "A"; > }; > > - gpiob { > + gpiob@30 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x30 0x10>; > bank-name = "B"; > }; > > - gpioc { > + gpioc@40 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x40 0x10>; > @@ -78,7 +78,7 @@ > }; > }; > > - tpm { > + tpm@fed40000 { > reg = <0xfed40000 0x5000>; > compatible = "infineon,slb9635lpc"; > }; > diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts > index 478dece..e0da067 100644 > --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts > +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts > @@ -69,7 +69,7 @@ > }; > }; > > - pci { > + pci@0 { > compatible = "intel,pci-baytrail", "pci-x86"; > #address-cells = <3>; > #size-cells = <2>; > @@ -159,49 +159,49 @@ > compatible = "stmicro,n25q064a", > "spi-flash"; > memory-map = <0xff800000 0x00800000>; > - rw-mrc-cache { > + rw-mrc-cache@6f0000 { > label = "rw-mrc-cache"; > reg = <0x006f0000 0x00010000>; > }; > }; > }; > > - gpioa { > + gpioa@0 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0 0x20>; > bank-name = "A"; > }; > > - gpiob { > + gpiob@20 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x20 0x20>; > bank-name = "B"; > }; > > - gpioc { > + gpioc@40 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x40 0x20>; > bank-name = "C"; > }; > > - gpiod { > + gpiod@60 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x60 0x20>; > bank-name = "D"; > }; > > - gpioe { > + gpioe@80 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x80 0x20>; > bank-name = "E"; > }; > > - gpiof { > + gpiof@a0 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0xA0 0x20>; > @@ -268,10 +268,10 @@ > }; > > microcode { > - update@0 { > + update_0 { > #include "microcode/m0130673322.dtsi" > }; > - update@1 { > + update_1 { > #include "microcode/m0130679901.dtsi" > }; > }; > diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts > index d415566..b2637b8 100644 > --- a/arch/x86/dts/cougarcanyon2.dts > +++ b/arch/x86/dts/cougarcanyon2.dts > @@ -29,19 +29,19 @@ > }; > > microcode { > - update@0 { > + update_0 { > #include "microcode/m12306a2_00000008.dtsi" > }; > - update@1 { > + update_1 { > #include "microcode/m12306a4_00000007.dtsi" > }; > - update@2 { > + update_2 { > #include "microcode/m12306a5_00000007.dtsi" > }; > - update@3 { > + update_3 { > #include "microcode/m12306a8_00000010.dtsi" > }; > - update@4 { > + update_4 { > #include "microcode/m12306a9_0000001b.dtsi" > }; > }; > @@ -51,7 +51,7 @@ > fsp,enable-ht; > }; > > - pci { > + pci@0 { > #address-cells = <3>; > #size-cells = <2>; > compatible = "pci-x86"; > @@ -78,21 +78,21 @@ > }; > }; > > - gpioa { > + gpioa@10 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0 0x10>; > bank-name = "A"; > }; > > - gpiob { > + gpiob@30 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x30 0x10>; > bank-name = "B"; > }; > > - gpioc { > + gpioc@40 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x40 0x10>; > diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts > index 337513b..4cd9b4d 100644 > --- a/arch/x86/dts/crownbay.dts > +++ b/arch/x86/dts/crownbay.dts > @@ -59,12 +59,12 @@ > }; > > microcode { > - update@0 { > + update_0 { > #include "microcode/m0220661105_cv.dtsi" > }; > }; > > - pci { > + pci@0 { > #address-cells = <3>; > #size-cells = <2>; > compatible = "pci-x86"; > @@ -227,14 +227,14 @@ > }; > }; > > - gpioa { > + gpioa@0 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0 0x20>; > bank-name = "A"; > }; > > - gpiob { > + gpiob@20 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x20 0x20>; > diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts > index 21c3641..f2cd456 100644 > --- a/arch/x86/dts/galileo.dts > +++ b/arch/x86/dts/galileo.dts > @@ -56,7 +56,7 @@ > dram-faw = <0x00009c40>; > }; > > - pci { > + pci@0 { > #address-cells = <3>; > #size-cells = <2>; > compatible = "pci-x86"; > @@ -128,21 +128,21 @@ > compatible = "winbond,w25q64", > "spi-flash"; > memory-map = <0xff800000 0x00800000>; > - rw-mrc-cache { > + rw-mrc-cache@10000 { > label = "rw-mrc-cache"; > reg = <0x00010000 0x00010000>; > }; > }; > }; > > - gpioa { > + gpioa@0 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0 0x20>; > bank-name = "A"; > }; > > - gpiob { > + gpiob@20 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x20 0x20>; > diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts > index 60bd05a..37ab8ae 100644 > --- a/arch/x86/dts/minnowmax.dts > +++ b/arch/x86/dts/minnowmax.dts > @@ -31,7 +31,7 @@ > compatible = "intel,x86-pinctrl"; > > /* GPIO E0 */ > - soc_gpio_s5_0@0 { > + soc_gpio_s5_0 { > gpio-offset = <0x80 0>; > pad-offset = <0x1d0>; > mode-gpio; > @@ -40,7 +40,7 @@ > }; > > /* GPIO E1 */ > - soc_gpio_s5_1@0 { > + soc_gpio_s5_1 { > gpio-offset = <0x80 1>; > pad-offset = <0x210>; > mode-gpio; > @@ -49,7 +49,7 @@ > }; > > /* GPIO E2 */ > - soc_gpio_s5_2@0 { > + soc_gpio_s5_2 { > gpio-offset = <0x80 2>; > pad-offset = <0x1e0>; > mode-gpio; > @@ -57,7 +57,7 @@ > direction = <PIN_OUTPUT>; > }; > > - pin_usb_host_en0@0 { > + pin_usb_host_en0 { > gpio-offset = <0x80 8>; > pad-offset = <0x260>; > mode-gpio; > @@ -65,7 +65,7 @@ > direction = <PIN_OUTPUT>; > }; > > - pin_usb_host_en1@0 { > + pin_usb_host_en1 { > gpio-offset = <0x80 9>; > pad-offset = <0x250>; > mode-gpio; > @@ -98,7 +98,7 @@ > > }; > > - pci { > + pci@0 { > compatible = "intel,pci-baytrail", "pci-x86"; > #address-cells = <3>; > #size-cells = <2>; > @@ -188,49 +188,49 @@ > compatible = "stmicro,n25q064a", > "spi-flash"; > memory-map = <0xff800000 0x00800000>; > - rw-mrc-cache { > + rw-mrc-cache@6f0000 { > label = "rw-mrc-cache"; > reg = <0x006f0000 0x00010000>; > }; > }; > }; > > - gpioa { > + gpioa@0 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0 0x20>; > bank-name = "A"; > }; > > - gpiob { > + gpiob@20 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x20 0x20>; > bank-name = "B"; > }; > > - gpioc { > + gpioc@40 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x40 0x20>; > bank-name = "C"; > }; > > - gpiod { > + gpiod@60 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x60 0x20>; > bank-name = "D"; > }; > > - gpioe { > + gpioe@80 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0x80 0x20>; > bank-name = "E"; > }; > > - gpiof { > + gpiof@a0 { > compatible = "intel,ich6-gpio"; > u-boot,dm-pre-reloc; > reg = <0xA0 0x20>; > @@ -296,10 +296,10 @@ > }; > > microcode { > - update@0 { > + update_0 { > #include "microcode/m0130673322.dtsi" > }; > - update@1 { > + update_1 { > #include "microcode/m0130679901.dtsi" > }; > }; > diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts > index 9c3f2a0..3d81e9d 100644 > --- a/arch/x86/dts/qemu-x86_i440fx.dts > +++ b/arch/x86/dts/qemu-x86_i440fx.dts > @@ -42,7 +42,7 @@ > clock-frequency = <1000000000>; > }; > > - pci { > + pci@0 { > compatible = "pci-x86"; > #address-cells = <3>; > #size-cells = <2>; > diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts > index 5d601b3..931c258 100644 > --- a/arch/x86/dts/qemu-x86_q35.dts > +++ b/arch/x86/dts/qemu-x86_q35.dts > @@ -53,7 +53,7 @@ > clock-frequency = <1000000000>; > }; > > - pci { > + pci@0 { > compatible = "pci-x86"; > #address-cells = <3>; > #size-cells = <2>; > diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi > index 1797e04..9b09d7e 100644 > --- a/arch/x86/dts/rtc.dtsi > +++ b/arch/x86/dts/rtc.dtsi > @@ -1,5 +1,5 @@ > / { > - rtc { > + rtc@70 { > compatible = "motorola,mc146818"; > u-boot,dm-pre-reloc; > reg = <0x70 2>; > diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi > index 54c3faf..02be132 100644 > --- a/arch/x86/dts/serial.dtsi > +++ b/arch/x86/dts/serial.dtsi > @@ -1,5 +1,5 @@ > / { > - serial: serial { > + serial: serial@3f8 { > compatible = "ns16550"; > reg = <0x3f8 8>; > reg-shift = <0>; > diff --git a/arch/x86/dts/skeleton.dtsi b/arch/x86/dts/skeleton.dtsi > index b41d241..a20da0a 100644 > --- a/arch/x86/dts/skeleton.dtsi > +++ b/arch/x86/dts/skeleton.dtsi > @@ -9,5 +9,5 @@ > #size-cells = <1>; > chosen { }; > aliases { }; > - memory { device_type = "memory"; reg = <0 0>; }; > + memory@0 { device_type = "memory"; reg = <0 0>; }; > }; > diff --git a/doc/device-tree-bindings/pmic/sandbox.txt b/doc/device-tree-bindings/pmic/sandbox.txt > index d84c977..c1bef4c 100644 > --- a/doc/device-tree-bindings/pmic/sandbox.txt > +++ b/doc/device-tree-bindings/pmic/sandbox.txt > @@ -24,7 +24,7 @@ Optional subnodes: > > Example: > > -sandbox_pmic { > +sandbox_pmic@40 { > compatible = "sandbox,pmic"; > reg = <0x40>; > > diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c > index e3229ef..e3e2835 100644 > --- a/drivers/misc/cros_ec.c > +++ b/drivers/misc/cros_ec.c > @@ -1038,11 +1038,11 @@ int cros_ec_decode_ec_flash(const void *blob, int node, > const char *name = fdt_get_name(blob, node, NULL); > enum ec_flash_region region; > > - if (0 == strcmp(name, "ro")) { > + if (0 == strcmp(name, "ro@0")) { > region = EC_FLASH_REGION_RO; > - } else if (0 == strcmp(name, "rw")) { > + } else if (0 == strcmp(name, "rw@10000")) { > region = EC_FLASH_REGION_RW; > - } else if (0 == strcmp(name, "wp-ro")) { > + } else if (0 == strcmp(name, "wp-ro@f000")) { > region = EC_FLASH_REGION_WP_RO; > } else { > debug("Unknown EC flash region name '%s'\n", name); [snip] Regards, Bin
Hello Bin Am 18.04.2016 um 04:21 schrieb Bin Meng: > Hi Heiko, > > On Fri, Apr 15, 2016 at 6:57 PM, Heiko Schocher <hs@denx.de> wrote: >> Fix following DTC warnings for all x86 boards. >> >> There was a warning like: >> Warning (unit_address_vs_reg): Node /microcode/update@0 has a unit name, but no reg property >> Warning (unit_address_vs_reg): Node /microcode/update@1 has a unit name, but no reg property >> >> I replaced "udpate@" with "update_". Please test >> this patch >> >> Signed-off-by: Heiko Schocher <hs@denx.de> >> --- >> This warnings pop up with the DTC compiler: >> $ /tmp/dtc/dtc -v >> Version: DTC 1.4.1-gbeef80b8 >> >> This fixes the compile warnings for: >> https://travis-ci.org/u-boot/u-boot/jobs/122880432 >> >> see: >> https://travis-ci.org/hsdenx/u-boot/jobs/123281030 >> >> Tested with sandbox, following steps work as before: >> >> make sandbox_defconfig >> make >> ./u-boot -d u-boot.dtb >> >> but "ut all" drops warnings ... but this patch introduced >> no new warnings ... >> >> output of test/py : >> (deleted the long lines) >> >> +make O=/home/hs/zug/travis/u-boot.git/build-sandbox -s sandbox_defconfig >> +make O=/home/hs/zug/travis/u-boot.git/build-sandbox -s -j8 >> platform linux2 -- Python 2.7.10, pytest-2.8.7, py-1.4.31, pluggy-0.3.1 >> rootdir: /home/hs/zug/travis/u-boot.git, inifile: >> collected 204 items >> >> test/py/tests/test_000_version.py . >> test/py/tests/test_dfu.py s >> test/py/tests/test_env.py ........ >> test/py/tests/test_help.py . >> test/py/tests/test_hush_if_test.py ....................................................... >> test/py/tests/test_md.py .. >> test/py/tests/test_net.py .ssss >> test/py/tests/test_sandbox_exit.py .. >> test/py/tests/test_shell_basics.py .... >> test/py/tests/test_sleep.py . >> test/py/tests/test_ums.py s >> test/py/tests/test_unknown_cmd.py . >> test/py/tests/test_ut.py ......................................................................................F................................... >> >> u_boot_console = <u_boot_console_sandbox.ConsoleSandbox object at 0x7f68ce2852d0>, ut_subtest = 'dm spi_flash' >> >> def test_ut(u_boot_console, ut_subtest): >> """Execute a "ut" subtest.""" >> >> output = u_boot_console.run_command('ut ' + ut_subtest) >>> assert output.endswith('Failures: 0') >> E assert <built-in method endswith of str object at 0x7f68cf10e6d0>('Failures: 0') >> E + where <built-in method endswith of str object at 0x7f68cf10e6d0> = 'Test: dm_test_spi_flash\r\r\n2097152 bytes written in 24 ms (83.3 MiB/s)\r\r\nSF: Detected M25P16 with page size 256 ...d_list( "sb save hostfs - 0 spi.bin 200000;" "sf probe;" "sf test 0 10000", -1, 0): Expected 0, got 1\r\r\nFailures: 1'.endswith >> >> test/py/tests/test_ut.py:29: AssertionError >> >> => ut dm spi_flash >> Test: dm_test_spi_flash >> 2097152 bytes written in 24 ms (83.3 MiB/s) >> SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB >> SPI flash test: >> SF: Timeout! >> Erase failed >> Test failed >> ../test/dm/sf.c:34, dm_test_spi_flash(): 0 == run_command_list( "sb save hostfs - 0 spi.bin 200000;" "sf probe;" "sf test 0 10000", -1, 0): Expected 0, got 1 >> Failures: 1 >> => >> >> This error is also without this patch ... may I find >> time to fix it too... >> >> >> arch/sandbox/dts/sandbox.dts | 30 ++++++++-------- >> arch/sandbox/dts/test.dts | 58 +++++++++++++++---------------- >> arch/x86/dts/bayleybay.dts | 22 ++++++------ >> arch/x86/dts/broadwell_som-6896.dts | 2 +- >> arch/x86/dts/chromebook_link.dts | 22 ++++++------ >> arch/x86/dts/chromebook_samus.dts | 30 ++++++++-------- >> arch/x86/dts/chromebox_panther.dts | 12 +++---- >> arch/x86/dts/conga-qeval20-qa3-e3845.dts | 20 +++++------ >> arch/x86/dts/cougarcanyon2.dts | 18 +++++----- >> arch/x86/dts/crownbay.dts | 8 ++--- >> arch/x86/dts/galileo.dts | 8 ++--- >> arch/x86/dts/minnowmax.dts | 30 ++++++++-------- >> arch/x86/dts/qemu-x86_i440fx.dts | 2 +- >> arch/x86/dts/qemu-x86_q35.dts | 2 +- >> arch/x86/dts/rtc.dtsi | 2 +- >> arch/x86/dts/serial.dtsi | 2 +- >> arch/x86/dts/skeleton.dtsi | 2 +- >> doc/device-tree-bindings/pmic/sandbox.txt | 2 +- >> drivers/misc/cros_ec.c | 6 ++-- >> include/sandbox-adc.h | 2 +- >> test/dm/bus.c | 4 +-- >> test/dm/eth.c | 4 +-- >> test/dm/gpio.c | 2 +- >> test/dm/pmic.c | 4 +-- >> test/dm/spmi.c | 2 +- >> test/dm/test-fdt.c | 16 ++++----- >> 26 files changed, 156 insertions(+), 156 deletions(-) >> [...] >> diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts >> index 4ea9262..207e7e0 100644 >> --- a/arch/x86/dts/bayleybay.dts >> +++ b/arch/x86/dts/bayleybay.dts [...] >> @@ -155,49 +155,49 @@ >> compatible = "winbond,w25q64dw", >> "spi-flash"; >> memory-map = <0xff800000 0x00800000>; >> - rw-mrc-cache { >> + rw-mrc-cache@6e0000 { >> label = "rw-mrc-cache"; >> reg = <0x006e0000 0x00010000>; >> }; >> }; >> }; >> >> - gpioa { >> + gpioa@0 { > > What about just gpio@0? I just added the missing @offset ... I am fine renaming it also from gpioa to just gpio ... > >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0 0x20>; >> bank-name = "A"; >> }; >> >> - gpiob { >> + gpiob@20 { > > and gpio@20? I am fine with it ... >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x20 0x20>; >> bank-name = "B"; >> }; >> >> - gpioc { >> + gpioc@40 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x40 0x20>; >> bank-name = "C"; >> }; >> >> - gpiod { >> + gpiod@60 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x60 0x20>; >> bank-name = "D"; >> }; >> >> - gpioe { >> + gpioe@80 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x80 0x20>; >> bank-name = "E"; >> }; >> >> - gpiof { >> + gpiof@a0 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0xA0 0x20>; >> @@ -245,13 +245,13 @@ >> }; >> >> microcode { >> - update@0 { >> + update_0 { > > update0? Ok. >> #include "microcode/m0230671117.dtsi" >> }; >> - update@1 { >> + update_1 { >> #include "microcode/m0130673322.dtsi" >> }; >> - update@2 { >> + update_2 { >> #include "microcode/m0130679901.dtsi" >> }; >> }; >> diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts >> index 4bb0a34..674d09a 100644 >> --- a/arch/x86/dts/broadwell_som-6896.dts >> +++ b/arch/x86/dts/broadwell_som-6896.dts >> @@ -21,7 +21,7 @@ >> stdout-path = "/serial"; >> }; >> >> - pci { >> + pci@0 { >> compatible = "pci-x86"; >> #address-cells = <3>; >> #size-cells = <2>; >> diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts >> index fb1b31d..41aae38 100644 >> --- a/arch/x86/dts/chromebook_link.dts >> +++ b/arch/x86/dts/chromebook_link.dts >> @@ -64,7 +64,7 @@ >> intel,duplicate-por; >> }; >> >> - pch_pinctrl { >> + pch_pinctrl@0 { >> compatible = "intel,x86-pinctrl"; >> u-boot,dm-pre-reloc; >> reg = <0 0>; >> @@ -217,7 +217,7 @@ >> >> }; >> >> - pci { >> + pci@0 { >> compatible = "pci-x86"; >> #address-cells = <3>; >> #size-cells = <2>; >> @@ -235,7 +235,7 @@ >> spd { >> #address-cells = <1>; >> #size-cells = <0>; >> - elpida_4Gb_1600_x16 { >> + elpida_4Gb_1600_x16@0 { >> reg = <0>; >> data = [92 10 0b 03 04 19 02 02 >> 03 52 01 08 0a 00 fe 00 >> @@ -270,7 +270,7 @@ >> 00 00 00 00 00 00 00 00 >> 00 00 00 00 00 00 00 00]; >> }; >> - samsung_4Gb_1600_1.35v_x16 { >> + samsung_4Gb_1600_1.35v_x16@1 { >> reg = <1>; >> data = [92 11 0b 03 04 19 02 02 >> 03 11 01 08 0a 00 fe 00 >> @@ -305,7 +305,7 @@ >> 00 00 00 00 00 00 00 00 >> 00 00 00 00 00 00 00 00]; >> }; >> - micron_4Gb_1600_1.35v_x16 { >> + micron_4Gb_1600_1.35v_x16@2 { >> reg = <2>; >> data = [92 11 0b 03 04 19 02 02 >> 03 11 01 08 0a 00 fe 00 >> @@ -397,14 +397,14 @@ >> compatible = "winbond,w25q64", >> "spi-flash"; >> memory-map = <0xff800000 0x00800000>; >> - rw-mrc-cache { >> + rw-mrc-cache@3e0000 { >> label = "rw-mrc-cache"; >> reg = <0x003e0000 0x00010000>; >> }; >> }; >> }; >> >> - gpio_a: gpioa { >> + gpio_a: gpioa@0 { > > ditto Yes, we should solve this in a common way ... could you test my changes on a hw? But what is with the reference "gpio_a" ? >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> #gpio-cells = <2>; >> @@ -413,7 +413,7 @@ >> bank-name = "A"; >> }; >> >> - gpio_b: gpiob { >> + gpio_b: gpiob@30 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> #gpio-cells = <2>; >> @@ -422,7 +422,7 @@ >> bank-name = "B"; >> }; >> >> - gpio_c: gpioc { >> + gpio_c: gpioc@40 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> #gpio-cells = <2>; >> @@ -471,13 +471,13 @@ >> }; >> }; >> >> - tpm { >> + tpm@fed40000 { >> reg = <0xfed40000 0x5000>; >> compatible = "infineon,slb9635lpc"; >> }; >> >> microcode { >> - update@0 { >> + update_1 { > > This should be update0. Oh, typo, thanks. >> #include "microcode/m12306a9_0000001b.dtsi" >> }; >> }; >> diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts >> index 5dd3e57..103e26f 100644 >> --- a/arch/x86/dts/chromebook_samus.dts >> +++ b/arch/x86/dts/chromebook_samus.dts >> @@ -65,7 +65,7 @@ >> intel,duplicate-por; >> }; >> >> - pch_pinctrl { >> + pch_pinctrl@0 { >> compatible = "intel,x86-broadwell-pinctrl"; >> u-boot,dm-pre-reloc; >> reg = <0 0>; >> @@ -131,7 +131,7 @@ >> pirq-apic = <PIRQ_APIC_ROUTE>; >> }; >> >> - soc_gpio@0 { >> + soc_gpio { >> config = >> <0 &gpio_unused 0>, /* unused */ >> <1 &gpio_unused 0>, /* unused */ >> @@ -231,7 +231,7 @@ >> }; >> }; >> >> - pci { >> + pci@0 { >> compatible = "pci-x86"; >> #address-cells = <3>; >> #size-cells = <2>; >> @@ -249,7 +249,7 @@ >> spd { >> #address-cells = <1>; >> #size-cells = <0>; >> - samsung_4 { >> + samsung_4@6 { >> reg = <6>; >> data = [91 20 f1 03 04 11 05 0b >> 03 11 01 08 0a 00 50 01 >> @@ -284,7 +284,7 @@ >> 00 00 00 00 00 00 00 00 >> 00 00 00 00 00 00 00 00]; >> }; >> - hynix-h9ccnnnbltmlar-ntm-lpddr3-32 { >> + hynix-h9ccnnnbltmlar-ntm-lpddr3-32@8 { >> /* >> * banks 8, ranks 2, rows 14, >> * columns 10, density 4096 mb, x32 >> @@ -323,7 +323,7 @@ >> 00 00 00 00 00 00 00 00 >> 00 00 00 00 00 00 00 00]; >> }; >> - samsung_8 { >> + samsung_8@10 { >> reg = <10>; >> data = [91 20 f1 03 04 12 05 0a >> 03 11 01 08 0a 00 50 01 >> @@ -358,7 +358,7 @@ >> 00 00 00 00 00 00 00 00 >> 00 00 00 00 00 00 00 00]; >> }; >> - hynix-h9ccnnnbltmlar-ntm-lpddr3-16 { >> + hynix-h9ccnnnbltmlar-ntm-lpddr3-16@12 { >> /* >> * banks 8, ranks 2, rows 14, >> * columns 11, density 4096 mb, x16 >> @@ -397,7 +397,7 @@ >> 00 00 00 00 00 00 00 00 >> 00 00 00 00 00 00 00 00]; >> }; >> - hynix-h9ccnnncltmlar-lpddr3 { >> + hynix-h9ccnnncltmlar-lpddr3@13 { >> /* >> * banks 8, ranks 2, rows 15, >> * columns 11, density 8192 mb, x16 >> @@ -436,7 +436,7 @@ >> 00 00 00 00 00 00 00 00 >> 00 00 00 00 00 00 00 00]; >> }; >> - elpida-edfb232a1ma { >> + elpida-edfb232a1ma@15 { >> /* >> * banks 8, ranks 2, rows 15, >> * columns 11, density 8192 mb, x16 >> @@ -539,14 +539,14 @@ >> compatible = "winbond,w25q64", >> "spi-flash"; >> memory-map = <0xff800000 0x00800000>; >> - rw-mrc-cache { >> + rw-mrc-cache@3e0000 { >> label = "rw-mrc-cache"; >> reg = <0x003e0000 0x00010000>; >> }; >> }; >> }; >> >> - gpio_a: gpioa { >> + gpio_a: gpioa@0 { >> compatible = "intel,broadwell-gpio"; >> u-boot,dm-pre-reloc; >> #gpio-cells = <2>; >> @@ -555,7 +555,7 @@ >> bank-name = "A"; >> }; >> >> - gpio_b: gpiob { >> + gpio_b: gpiob@1 { >> compatible = "intel,broadwell-gpio"; >> u-boot,dm-pre-reloc; >> #gpio-cells = <2>; >> @@ -564,7 +564,7 @@ >> bank-name = "B"; >> }; >> >> - gpio_c: gpioc { >> + gpio_c: gpioc@2 { >> compatible = "intel,broadwell-gpio"; >> u-boot,dm-pre-reloc; >> #gpio-cells = <2>; >> @@ -614,13 +614,13 @@ >> }; >> }; >> >> - tpm { >> + tpm@fed40000 { >> reg = <0xfed40000 0x5000>; >> compatible = "infineon,slb9635lpc"; >> }; >> >> microcode { >> - update@0 { >> + update_1 { > > This should be update0. > >> #include "microcode/mc0306d4_00000018.dtsi" >> }; >> }; >> diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts >> index 480b366..4f88778 100644 >> --- a/arch/x86/dts/chromebox_panther.dts >> +++ b/arch/x86/dts/chromebox_panther.dts >> @@ -22,7 +22,7 @@ >> stdout-path = "/serial"; >> }; >> >> - pci { >> + pci@0 { >> compatible = "pci-x86"; >> #address-cells = <3>; >> #size-cells = <2>; >> @@ -48,28 +48,28 @@ >> compatible = "winbond,w25q64", >> "spi-flash"; >> memory-map = <0xff800000 0x00800000>; >> - rw-mrc-cache { >> + rw-mrc-cache@3e0000 { >> label = "rw-mrc-cache"; >> reg = <0x003e0000 0x00010000>; >> }; >> }; >> }; >> >> - gpioa { >> + gpioa@0 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0 0x10>; >> bank-name = "A"; >> }; >> >> - gpiob { >> + gpiob@30 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x30 0x10>; >> bank-name = "B"; >> }; >> >> - gpioc { >> + gpioc@40 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x40 0x10>; >> @@ -78,7 +78,7 @@ >> }; >> }; >> >> - tpm { >> + tpm@fed40000 { >> reg = <0xfed40000 0x5000>; >> compatible = "infineon,slb9635lpc"; >> }; >> diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts >> index 478dece..e0da067 100644 >> --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts >> +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts >> @@ -69,7 +69,7 @@ >> }; >> }; >> >> - pci { >> + pci@0 { >> compatible = "intel,pci-baytrail", "pci-x86"; >> #address-cells = <3>; >> #size-cells = <2>; >> @@ -159,49 +159,49 @@ >> compatible = "stmicro,n25q064a", >> "spi-flash"; >> memory-map = <0xff800000 0x00800000>; >> - rw-mrc-cache { >> + rw-mrc-cache@6f0000 { >> label = "rw-mrc-cache"; >> reg = <0x006f0000 0x00010000>; >> }; >> }; >> }; >> >> - gpioa { >> + gpioa@0 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0 0x20>; >> bank-name = "A"; >> }; >> >> - gpiob { >> + gpiob@20 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x20 0x20>; >> bank-name = "B"; >> }; >> >> - gpioc { >> + gpioc@40 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x40 0x20>; >> bank-name = "C"; >> }; >> >> - gpiod { >> + gpiod@60 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x60 0x20>; >> bank-name = "D"; >> }; >> >> - gpioe { >> + gpioe@80 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x80 0x20>; >> bank-name = "E"; >> }; >> >> - gpiof { >> + gpiof@a0 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0xA0 0x20>; >> @@ -268,10 +268,10 @@ >> }; >> >> microcode { >> - update@0 { >> + update_0 { >> #include "microcode/m0130673322.dtsi" >> }; >> - update@1 { >> + update_1 { >> #include "microcode/m0130679901.dtsi" >> }; >> }; >> diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts >> index d415566..b2637b8 100644 >> --- a/arch/x86/dts/cougarcanyon2.dts >> +++ b/arch/x86/dts/cougarcanyon2.dts >> @@ -29,19 +29,19 @@ >> }; >> >> microcode { >> - update@0 { >> + update_0 { >> #include "microcode/m12306a2_00000008.dtsi" >> }; >> - update@1 { >> + update_1 { >> #include "microcode/m12306a4_00000007.dtsi" >> }; >> - update@2 { >> + update_2 { >> #include "microcode/m12306a5_00000007.dtsi" >> }; >> - update@3 { >> + update_3 { >> #include "microcode/m12306a8_00000010.dtsi" >> }; >> - update@4 { >> + update_4 { >> #include "microcode/m12306a9_0000001b.dtsi" >> }; >> }; >> @@ -51,7 +51,7 @@ >> fsp,enable-ht; >> }; >> >> - pci { >> + pci@0 { >> #address-cells = <3>; >> #size-cells = <2>; >> compatible = "pci-x86"; >> @@ -78,21 +78,21 @@ >> }; >> }; >> >> - gpioa { >> + gpioa@10 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0 0x10>; >> bank-name = "A"; >> }; >> >> - gpiob { >> + gpiob@30 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x30 0x10>; >> bank-name = "B"; >> }; >> >> - gpioc { >> + gpioc@40 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x40 0x10>; >> diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts >> index 337513b..4cd9b4d 100644 >> --- a/arch/x86/dts/crownbay.dts >> +++ b/arch/x86/dts/crownbay.dts >> @@ -59,12 +59,12 @@ >> }; >> >> microcode { >> - update@0 { >> + update_0 { >> #include "microcode/m0220661105_cv.dtsi" >> }; >> }; >> >> - pci { >> + pci@0 { >> #address-cells = <3>; >> #size-cells = <2>; >> compatible = "pci-x86"; >> @@ -227,14 +227,14 @@ >> }; >> }; >> >> - gpioa { >> + gpioa@0 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0 0x20>; >> bank-name = "A"; >> }; >> >> - gpiob { >> + gpiob@20 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x20 0x20>; >> diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts >> index 21c3641..f2cd456 100644 >> --- a/arch/x86/dts/galileo.dts >> +++ b/arch/x86/dts/galileo.dts >> @@ -56,7 +56,7 @@ >> dram-faw = <0x00009c40>; >> }; >> >> - pci { >> + pci@0 { >> #address-cells = <3>; >> #size-cells = <2>; >> compatible = "pci-x86"; >> @@ -128,21 +128,21 @@ >> compatible = "winbond,w25q64", >> "spi-flash"; >> memory-map = <0xff800000 0x00800000>; >> - rw-mrc-cache { >> + rw-mrc-cache@10000 { >> label = "rw-mrc-cache"; >> reg = <0x00010000 0x00010000>; >> }; >> }; >> }; >> >> - gpioa { >> + gpioa@0 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0 0x20>; >> bank-name = "A"; >> }; >> >> - gpiob { >> + gpiob@20 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x20 0x20>; >> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts >> index 60bd05a..37ab8ae 100644 >> --- a/arch/x86/dts/minnowmax.dts >> +++ b/arch/x86/dts/minnowmax.dts >> @@ -31,7 +31,7 @@ >> compatible = "intel,x86-pinctrl"; >> >> /* GPIO E0 */ >> - soc_gpio_s5_0@0 { >> + soc_gpio_s5_0 { >> gpio-offset = <0x80 0>; >> pad-offset = <0x1d0>; >> mode-gpio; >> @@ -40,7 +40,7 @@ >> }; >> >> /* GPIO E1 */ >> - soc_gpio_s5_1@0 { >> + soc_gpio_s5_1 { >> gpio-offset = <0x80 1>; >> pad-offset = <0x210>; >> mode-gpio; >> @@ -49,7 +49,7 @@ >> }; >> >> /* GPIO E2 */ >> - soc_gpio_s5_2@0 { >> + soc_gpio_s5_2 { >> gpio-offset = <0x80 2>; >> pad-offset = <0x1e0>; >> mode-gpio; >> @@ -57,7 +57,7 @@ >> direction = <PIN_OUTPUT>; >> }; >> >> - pin_usb_host_en0@0 { >> + pin_usb_host_en0 { >> gpio-offset = <0x80 8>; >> pad-offset = <0x260>; >> mode-gpio; >> @@ -65,7 +65,7 @@ >> direction = <PIN_OUTPUT>; >> }; >> >> - pin_usb_host_en1@0 { >> + pin_usb_host_en1 { >> gpio-offset = <0x80 9>; >> pad-offset = <0x250>; >> mode-gpio; >> @@ -98,7 +98,7 @@ >> >> }; >> >> - pci { >> + pci@0 { >> compatible = "intel,pci-baytrail", "pci-x86"; >> #address-cells = <3>; >> #size-cells = <2>; >> @@ -188,49 +188,49 @@ >> compatible = "stmicro,n25q064a", >> "spi-flash"; >> memory-map = <0xff800000 0x00800000>; >> - rw-mrc-cache { >> + rw-mrc-cache@6f0000 { >> label = "rw-mrc-cache"; >> reg = <0x006f0000 0x00010000>; >> }; >> }; >> }; >> >> - gpioa { >> + gpioa@0 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0 0x20>; >> bank-name = "A"; >> }; >> >> - gpiob { >> + gpiob@20 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x20 0x20>; >> bank-name = "B"; >> }; >> >> - gpioc { >> + gpioc@40 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x40 0x20>; >> bank-name = "C"; >> }; >> >> - gpiod { >> + gpiod@60 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x60 0x20>; >> bank-name = "D"; >> }; >> >> - gpioe { >> + gpioe@80 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0x80 0x20>; >> bank-name = "E"; >> }; >> >> - gpiof { >> + gpiof@a0 { >> compatible = "intel,ich6-gpio"; >> u-boot,dm-pre-reloc; >> reg = <0xA0 0x20>; >> @@ -296,10 +296,10 @@ >> }; >> >> microcode { >> - update@0 { >> + update_0 { >> #include "microcode/m0130673322.dtsi" >> }; >> - update@1 { >> + update_1 { >> #include "microcode/m0130679901.dtsi" >> }; >> }; >> diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts >> index 9c3f2a0..3d81e9d 100644 >> --- a/arch/x86/dts/qemu-x86_i440fx.dts >> +++ b/arch/x86/dts/qemu-x86_i440fx.dts >> @@ -42,7 +42,7 @@ >> clock-frequency = <1000000000>; >> }; >> >> - pci { >> + pci@0 { >> compatible = "pci-x86"; >> #address-cells = <3>; >> #size-cells = <2>; >> diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts >> index 5d601b3..931c258 100644 >> --- a/arch/x86/dts/qemu-x86_q35.dts >> +++ b/arch/x86/dts/qemu-x86_q35.dts >> @@ -53,7 +53,7 @@ >> clock-frequency = <1000000000>; >> }; >> >> - pci { >> + pci@0 { >> compatible = "pci-x86"; >> #address-cells = <3>; >> #size-cells = <2>; >> diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi >> index 1797e04..9b09d7e 100644 >> --- a/arch/x86/dts/rtc.dtsi >> +++ b/arch/x86/dts/rtc.dtsi >> @@ -1,5 +1,5 @@ >> / { >> - rtc { >> + rtc@70 { >> compatible = "motorola,mc146818"; >> u-boot,dm-pre-reloc; >> reg = <0x70 2>; >> diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi >> index 54c3faf..02be132 100644 >> --- a/arch/x86/dts/serial.dtsi >> +++ b/arch/x86/dts/serial.dtsi >> @@ -1,5 +1,5 @@ >> / { >> - serial: serial { >> + serial: serial@3f8 { >> compatible = "ns16550"; >> reg = <0x3f8 8>; >> reg-shift = <0>; >> diff --git a/arch/x86/dts/skeleton.dtsi b/arch/x86/dts/skeleton.dtsi >> index b41d241..a20da0a 100644 >> --- a/arch/x86/dts/skeleton.dtsi >> +++ b/arch/x86/dts/skeleton.dtsi >> @@ -9,5 +9,5 @@ >> #size-cells = <1>; >> chosen { }; >> aliases { }; >> - memory { device_type = "memory"; reg = <0 0>; }; >> + memory@0 { device_type = "memory"; reg = <0 0>; }; >> }; >> diff --git a/doc/device-tree-bindings/pmic/sandbox.txt b/doc/device-tree-bindings/pmic/sandbox.txt >> index d84c977..c1bef4c 100644 >> --- a/doc/device-tree-bindings/pmic/sandbox.txt >> +++ b/doc/device-tree-bindings/pmic/sandbox.txt >> @@ -24,7 +24,7 @@ Optional subnodes: >> >> Example: >> >> -sandbox_pmic { >> +sandbox_pmic@40 { >> compatible = "sandbox,pmic"; >> reg = <0x40>; >> >> diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c >> index e3229ef..e3e2835 100644 >> --- a/drivers/misc/cros_ec.c >> +++ b/drivers/misc/cros_ec.c >> @@ -1038,11 +1038,11 @@ int cros_ec_decode_ec_flash(const void *blob, int node, >> const char *name = fdt_get_name(blob, node, NULL); >> enum ec_flash_region region; >> >> - if (0 == strcmp(name, "ro")) { >> + if (0 == strcmp(name, "ro@0")) { >> region = EC_FLASH_REGION_RO; >> - } else if (0 == strcmp(name, "rw")) { >> + } else if (0 == strcmp(name, "rw@10000")) { >> region = EC_FLASH_REGION_RW; >> - } else if (0 == strcmp(name, "wp-ro")) { >> + } else if (0 == strcmp(name, "wp-ro@f000")) { >> region = EC_FLASH_REGION_WP_RO; >> } else { >> debug("Unknown EC flash region name '%s'\n", name); > > [snip] > > Regards, > Bin > Thanks for the review! bye, Heiko
On Fri, Apr 15, 2016 at 12:57:57PM +0200, Heiko Schocher wrote:
> Fix following DTC warnings for all x86 boards.
We're going to defer on this patch for now, thanks.
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 2ae4014..796de3a 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -34,13 +34,13 @@ #size-cells = <1>; /* Information for sandbox */ - ro { + ro@0 { reg = <0 0xf000>; }; - wp-ro { + wp-ro@f000 { reg = <0xf000 0x1000>; }; - rw { + rw@10000 { reg = <0x10000 0x10000>; }; }; @@ -64,7 +64,7 @@ host-raw-interface = "lo"; }; - gpio_a: gpios@0 { + gpio_a: gpios_0 { gpio-controller; compatible = "sandbox,gpio"; #gpio-cells = <1>; @@ -72,7 +72,7 @@ num-gpios = <20>; }; - gpio_b: gpios@1 { + gpio_b: gpios_1 { gpio-controller; compatible = "sandbox,gpio"; #gpio-cells = <2>; @@ -111,7 +111,7 @@ compatible = "sandbox,i2c-rtc"; }; }; - sandbox_pmic: sandbox_pmic { + sandbox_pmic: sandbox_pmic@40 { reg = <0x40>; }; }; @@ -123,7 +123,7 @@ yres = <768>; }; - pci: pci-controller { + pci: pci-controller@0 { compatible = "sandbox,pci"; device_type = "pci"; #address-cells = <3>; @@ -133,7 +133,7 @@ pci@1f,0 { compatible = "pci-generic"; reg = <0xf800 0 0 0 0>; - emul@1f,0 { + emul_1f,0 { compatible = "sandbox,swap-case"; }; }; @@ -154,7 +154,7 @@ }; }; - reset@1 { + reset { compatible = "sandbox,reset"; }; @@ -203,21 +203,21 @@ pinctrl-0 = <&pinctrl_serial0>; }; - usb@0 { + usb0 { compatible = "sandbox,usb"; status = "disabled"; hub { compatible = "sandbox,usb-hub"; #address-cells = <1>; #size-cells = <0>; - flash-stick { + flash-stick@0 { reg = <0>; compatible = "sandbox,usb-flash"; }; }; }; - usb@1 { + usb1 { compatible = "sandbox,usb"; hub { compatible = "usb-hub"; @@ -226,7 +226,7 @@ compatible = "sandbox,usb-hub"; #address-cells = <1>; #size-cells = <0>; - flash-stick { + flash-stick@0 { reg = <0>; compatible = "sandbox,usb-flash"; sandbox,filepath = "flash.bin"; @@ -235,12 +235,12 @@ }; }; - usb@2 { + usb2 { compatible = "sandbox,usb"; status = "disabled"; }; - spmi: spmi@0 { + spmi: spmi0 { compatible = "sandbox,spmi"; #address-cells = <0x1>; #size-cells = <0x1>; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 8930009..9c4e6e2 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -18,19 +18,19 @@ rtc0 = &rtc_0; rtc1 = &rtc_1; spi0 = "/spi@0"; - testfdt6 = "/e-test"; - testbus3 = "/some-bus"; - testfdt0 = "/some-bus/c-test@0"; - testfdt1 = "/some-bus/c-test@1"; - testfdt3 = "/b-test"; - testfdt5 = "/some-bus/c-test@5"; - testfdt8 = "/a-test"; + testfdt6 = "/e-test@3"; + testbus3 = "/some-bus@3"; + testfdt0 = "/some-bus@3/c-test@0"; + testfdt1 = "/some-bus@3/c-test@1"; + testfdt3 = "/b-test@3"; + testfdt5 = "/some-bus@3/c-test@5"; + testfdt8 = "/a-test@0"; usb0 = &usb_0; usb1 = &usb_1; usb2 = &usb_2; }; - a-test { + a-test@0 { reg = <0 1>; compatible = "denx,u-boot-fdt-test"; ping-expect = <0>; @@ -43,23 +43,23 @@ <&gpio_b 9 0xc 3 2 1>; }; - junk { + junk@1 { reg = <1 1>; compatible = "not,compatible"; }; - no-compatible { + no-compatible@2 { reg = <2 1>; }; - b-test { + b-test@3 { reg = <3 1>; compatible = "denx,u-boot-fdt-test"; ping-expect = <3>; ping-add = <3>; }; - some-bus { + some-bus@3 { #address-cells = <1>; #size-cells = <0>; compatible = "denx,u-boot-test-bus"; @@ -86,14 +86,14 @@ }; }; - d-test { + d-test@3 { reg = <3 1>; ping-expect = <6>; ping-add = <6>; compatible = "google,another-fdt-test"; }; - e-test { + e-test@3 { reg = <3 1>; ping-expect = <6>; ping-add = <6>; @@ -108,7 +108,7 @@ compatible = "denx,u-boot-fdt-test"; }; - clk@0 { + clk { compatible = "sandbox,clk"; }; @@ -124,7 +124,7 @@ fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>; }; - eth_3: sbe5 { + eth_3: sbe5@10005000 { compatible = "sandbox,eth"; reg = <0x10005000 0x1000>; fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x33>; @@ -184,12 +184,12 @@ }; }; - sandbox_pmic: sandbox_pmic { + sandbox_pmic: sandbox_pmic@40 { reg = <0x40>; }; }; - adc@0 { + adc { compatible = "sandbox,adc"; vdd-supply = <&buck2>; vss-microvolts = <0>; @@ -220,7 +220,7 @@ compatible = "sandbox,mmc"; }; - pci: pci-controller { + pci: pci-controller@0 { compatible = "sandbox,pci"; device_type = "pci"; #address-cells = <3>; @@ -230,7 +230,7 @@ pci@1f,0 { compatible = "pci-generic"; reg = <0xf800 0 0 0 0>; - emul@1f,0 { + emul_1f,0 { compatible = "sandbox,swap-case"; }; }; @@ -240,20 +240,20 @@ compatible = "sandbox,ram"; }; - reset@0 { + reset0 { compatible = "sandbox,warm-reset"; }; - reset@1 { + reset1 { compatible = "sandbox,reset"; }; - rproc_1: rproc@1 { + rproc_1: rproc1 { compatible = "sandbox,test-processor"; remoteproc-name = "remoteproc-test-dev1"; }; - rproc_2: rproc@2 { + rproc_2: rproc2 { compatible = "sandbox,test-processor"; internal-memory-mapped; remoteproc-name = "remoteproc-test-dev2"; @@ -296,21 +296,21 @@ u-boot,dm-pre-reloc; }; - usb_0: usb@0 { + usb_0: usb0 { compatible = "sandbox,usb"; status = "disabled"; hub { compatible = "sandbox,usb-hub"; #address-cells = <1>; #size-cells = <0>; - flash-stick { + flash-stick@0 { reg = <0>; compatible = "sandbox,usb-flash"; }; }; }; - usb_1: usb@1 { + usb_1: usb1 { compatible = "sandbox,usb"; hub { compatible = "usb-hub"; @@ -346,12 +346,12 @@ }; }; - usb_2: usb@2 { + usb_2: usb2 { compatible = "sandbox,usb"; status = "disabled"; }; - spmi: spmi@0 { + spmi: spmi0 { compatible = "sandbox,spmi"; #address-cells = <0x1>; #size-cells = <0x1>; diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 4ea9262..207e7e0 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -65,7 +65,7 @@ }; }; - pci { + pci@0 { compatible = "pci-x86"; #address-cells = <3>; #size-cells = <2>; @@ -155,49 +155,49 @@ compatible = "winbond,w25q64dw", "spi-flash"; memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { + rw-mrc-cache@6e0000 { label = "rw-mrc-cache"; reg = <0x006e0000 0x00010000>; }; }; }; - gpioa { + gpioa@0 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0 0x20>; bank-name = "A"; }; - gpiob { + gpiob@20 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x20 0x20>; bank-name = "B"; }; - gpioc { + gpioc@40 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x40 0x20>; bank-name = "C"; }; - gpiod { + gpiod@60 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x60 0x20>; bank-name = "D"; }; - gpioe { + gpioe@80 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x80 0x20>; bank-name = "E"; }; - gpiof { + gpiof@a0 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0xA0 0x20>; @@ -245,13 +245,13 @@ }; microcode { - update@0 { + update_0 { #include "microcode/m0230671117.dtsi" }; - update@1 { + update_1 { #include "microcode/m0130673322.dtsi" }; - update@2 { + update_2 { #include "microcode/m0130679901.dtsi" }; }; diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts index 4bb0a34..674d09a 100644 --- a/arch/x86/dts/broadwell_som-6896.dts +++ b/arch/x86/dts/broadwell_som-6896.dts @@ -21,7 +21,7 @@ stdout-path = "/serial"; }; - pci { + pci@0 { compatible = "pci-x86"; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index fb1b31d..41aae38 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -64,7 +64,7 @@ intel,duplicate-por; }; - pch_pinctrl { + pch_pinctrl@0 { compatible = "intel,x86-pinctrl"; u-boot,dm-pre-reloc; reg = <0 0>; @@ -217,7 +217,7 @@ }; - pci { + pci@0 { compatible = "pci-x86"; #address-cells = <3>; #size-cells = <2>; @@ -235,7 +235,7 @@ spd { #address-cells = <1>; #size-cells = <0>; - elpida_4Gb_1600_x16 { + elpida_4Gb_1600_x16@0 { reg = <0>; data = [92 10 0b 03 04 19 02 02 03 52 01 08 0a 00 fe 00 @@ -270,7 +270,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00]; }; - samsung_4Gb_1600_1.35v_x16 { + samsung_4Gb_1600_1.35v_x16@1 { reg = <1>; data = [92 11 0b 03 04 19 02 02 03 11 01 08 0a 00 fe 00 @@ -305,7 +305,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00]; }; - micron_4Gb_1600_1.35v_x16 { + micron_4Gb_1600_1.35v_x16@2 { reg = <2>; data = [92 11 0b 03 04 19 02 02 03 11 01 08 0a 00 fe 00 @@ -397,14 +397,14 @@ compatible = "winbond,w25q64", "spi-flash"; memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { + rw-mrc-cache@3e0000 { label = "rw-mrc-cache"; reg = <0x003e0000 0x00010000>; }; }; }; - gpio_a: gpioa { + gpio_a: gpioa@0 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; #gpio-cells = <2>; @@ -413,7 +413,7 @@ bank-name = "A"; }; - gpio_b: gpiob { + gpio_b: gpiob@30 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; #gpio-cells = <2>; @@ -422,7 +422,7 @@ bank-name = "B"; }; - gpio_c: gpioc { + gpio_c: gpioc@40 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; #gpio-cells = <2>; @@ -471,13 +471,13 @@ }; }; - tpm { + tpm@fed40000 { reg = <0xfed40000 0x5000>; compatible = "infineon,slb9635lpc"; }; microcode { - update@0 { + update_1 { #include "microcode/m12306a9_0000001b.dtsi" }; }; diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index 5dd3e57..103e26f 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -65,7 +65,7 @@ intel,duplicate-por; }; - pch_pinctrl { + pch_pinctrl@0 { compatible = "intel,x86-broadwell-pinctrl"; u-boot,dm-pre-reloc; reg = <0 0>; @@ -131,7 +131,7 @@ pirq-apic = <PIRQ_APIC_ROUTE>; }; - soc_gpio@0 { + soc_gpio { config = <0 &gpio_unused 0>, /* unused */ <1 &gpio_unused 0>, /* unused */ @@ -231,7 +231,7 @@ }; }; - pci { + pci@0 { compatible = "pci-x86"; #address-cells = <3>; #size-cells = <2>; @@ -249,7 +249,7 @@ spd { #address-cells = <1>; #size-cells = <0>; - samsung_4 { + samsung_4@6 { reg = <6>; data = [91 20 f1 03 04 11 05 0b 03 11 01 08 0a 00 50 01 @@ -284,7 +284,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00]; }; - hynix-h9ccnnnbltmlar-ntm-lpddr3-32 { + hynix-h9ccnnnbltmlar-ntm-lpddr3-32@8 { /* * banks 8, ranks 2, rows 14, * columns 10, density 4096 mb, x32 @@ -323,7 +323,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00]; }; - samsung_8 { + samsung_8@10 { reg = <10>; data = [91 20 f1 03 04 12 05 0a 03 11 01 08 0a 00 50 01 @@ -358,7 +358,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00]; }; - hynix-h9ccnnnbltmlar-ntm-lpddr3-16 { + hynix-h9ccnnnbltmlar-ntm-lpddr3-16@12 { /* * banks 8, ranks 2, rows 14, * columns 11, density 4096 mb, x16 @@ -397,7 +397,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00]; }; - hynix-h9ccnnncltmlar-lpddr3 { + hynix-h9ccnnncltmlar-lpddr3@13 { /* * banks 8, ranks 2, rows 15, * columns 11, density 8192 mb, x16 @@ -436,7 +436,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00]; }; - elpida-edfb232a1ma { + elpida-edfb232a1ma@15 { /* * banks 8, ranks 2, rows 15, * columns 11, density 8192 mb, x16 @@ -539,14 +539,14 @@ compatible = "winbond,w25q64", "spi-flash"; memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { + rw-mrc-cache@3e0000 { label = "rw-mrc-cache"; reg = <0x003e0000 0x00010000>; }; }; }; - gpio_a: gpioa { + gpio_a: gpioa@0 { compatible = "intel,broadwell-gpio"; u-boot,dm-pre-reloc; #gpio-cells = <2>; @@ -555,7 +555,7 @@ bank-name = "A"; }; - gpio_b: gpiob { + gpio_b: gpiob@1 { compatible = "intel,broadwell-gpio"; u-boot,dm-pre-reloc; #gpio-cells = <2>; @@ -564,7 +564,7 @@ bank-name = "B"; }; - gpio_c: gpioc { + gpio_c: gpioc@2 { compatible = "intel,broadwell-gpio"; u-boot,dm-pre-reloc; #gpio-cells = <2>; @@ -614,13 +614,13 @@ }; }; - tpm { + tpm@fed40000 { reg = <0xfed40000 0x5000>; compatible = "infineon,slb9635lpc"; }; microcode { - update@0 { + update_1 { #include "microcode/mc0306d4_00000018.dtsi" }; }; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 480b366..4f88778 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -22,7 +22,7 @@ stdout-path = "/serial"; }; - pci { + pci@0 { compatible = "pci-x86"; #address-cells = <3>; #size-cells = <2>; @@ -48,28 +48,28 @@ compatible = "winbond,w25q64", "spi-flash"; memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { + rw-mrc-cache@3e0000 { label = "rw-mrc-cache"; reg = <0x003e0000 0x00010000>; }; }; }; - gpioa { + gpioa@0 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0 0x10>; bank-name = "A"; }; - gpiob { + gpiob@30 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x30 0x10>; bank-name = "B"; }; - gpioc { + gpioc@40 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x40 0x10>; @@ -78,7 +78,7 @@ }; }; - tpm { + tpm@fed40000 { reg = <0xfed40000 0x5000>; compatible = "infineon,slb9635lpc"; }; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 478dece..e0da067 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -69,7 +69,7 @@ }; }; - pci { + pci@0 { compatible = "intel,pci-baytrail", "pci-x86"; #address-cells = <3>; #size-cells = <2>; @@ -159,49 +159,49 @@ compatible = "stmicro,n25q064a", "spi-flash"; memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { + rw-mrc-cache@6f0000 { label = "rw-mrc-cache"; reg = <0x006f0000 0x00010000>; }; }; }; - gpioa { + gpioa@0 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0 0x20>; bank-name = "A"; }; - gpiob { + gpiob@20 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x20 0x20>; bank-name = "B"; }; - gpioc { + gpioc@40 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x40 0x20>; bank-name = "C"; }; - gpiod { + gpiod@60 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x60 0x20>; bank-name = "D"; }; - gpioe { + gpioe@80 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x80 0x20>; bank-name = "E"; }; - gpiof { + gpiof@a0 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0xA0 0x20>; @@ -268,10 +268,10 @@ }; microcode { - update@0 { + update_0 { #include "microcode/m0130673322.dtsi" }; - update@1 { + update_1 { #include "microcode/m0130679901.dtsi" }; }; diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts index d415566..b2637b8 100644 --- a/arch/x86/dts/cougarcanyon2.dts +++ b/arch/x86/dts/cougarcanyon2.dts @@ -29,19 +29,19 @@ }; microcode { - update@0 { + update_0 { #include "microcode/m12306a2_00000008.dtsi" }; - update@1 { + update_1 { #include "microcode/m12306a4_00000007.dtsi" }; - update@2 { + update_2 { #include "microcode/m12306a5_00000007.dtsi" }; - update@3 { + update_3 { #include "microcode/m12306a8_00000010.dtsi" }; - update@4 { + update_4 { #include "microcode/m12306a9_0000001b.dtsi" }; }; @@ -51,7 +51,7 @@ fsp,enable-ht; }; - pci { + pci@0 { #address-cells = <3>; #size-cells = <2>; compatible = "pci-x86"; @@ -78,21 +78,21 @@ }; }; - gpioa { + gpioa@10 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0 0x10>; bank-name = "A"; }; - gpiob { + gpiob@30 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x30 0x10>; bank-name = "B"; }; - gpioc { + gpioc@40 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x40 0x10>; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 337513b..4cd9b4d 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -59,12 +59,12 @@ }; microcode { - update@0 { + update_0 { #include "microcode/m0220661105_cv.dtsi" }; }; - pci { + pci@0 { #address-cells = <3>; #size-cells = <2>; compatible = "pci-x86"; @@ -227,14 +227,14 @@ }; }; - gpioa { + gpioa@0 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0 0x20>; bank-name = "A"; }; - gpiob { + gpiob@20 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x20 0x20>; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 21c3641..f2cd456 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -56,7 +56,7 @@ dram-faw = <0x00009c40>; }; - pci { + pci@0 { #address-cells = <3>; #size-cells = <2>; compatible = "pci-x86"; @@ -128,21 +128,21 @@ compatible = "winbond,w25q64", "spi-flash"; memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { + rw-mrc-cache@10000 { label = "rw-mrc-cache"; reg = <0x00010000 0x00010000>; }; }; }; - gpioa { + gpioa@0 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0 0x20>; bank-name = "A"; }; - gpiob { + gpiob@20 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x20 0x20>; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 60bd05a..37ab8ae 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -31,7 +31,7 @@ compatible = "intel,x86-pinctrl"; /* GPIO E0 */ - soc_gpio_s5_0@0 { + soc_gpio_s5_0 { gpio-offset = <0x80 0>; pad-offset = <0x1d0>; mode-gpio; @@ -40,7 +40,7 @@ }; /* GPIO E1 */ - soc_gpio_s5_1@0 { + soc_gpio_s5_1 { gpio-offset = <0x80 1>; pad-offset = <0x210>; mode-gpio; @@ -49,7 +49,7 @@ }; /* GPIO E2 */ - soc_gpio_s5_2@0 { + soc_gpio_s5_2 { gpio-offset = <0x80 2>; pad-offset = <0x1e0>; mode-gpio; @@ -57,7 +57,7 @@ direction = <PIN_OUTPUT>; }; - pin_usb_host_en0@0 { + pin_usb_host_en0 { gpio-offset = <0x80 8>; pad-offset = <0x260>; mode-gpio; @@ -65,7 +65,7 @@ direction = <PIN_OUTPUT>; }; - pin_usb_host_en1@0 { + pin_usb_host_en1 { gpio-offset = <0x80 9>; pad-offset = <0x250>; mode-gpio; @@ -98,7 +98,7 @@ }; - pci { + pci@0 { compatible = "intel,pci-baytrail", "pci-x86"; #address-cells = <3>; #size-cells = <2>; @@ -188,49 +188,49 @@ compatible = "stmicro,n25q064a", "spi-flash"; memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { + rw-mrc-cache@6f0000 { label = "rw-mrc-cache"; reg = <0x006f0000 0x00010000>; }; }; }; - gpioa { + gpioa@0 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0 0x20>; bank-name = "A"; }; - gpiob { + gpiob@20 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x20 0x20>; bank-name = "B"; }; - gpioc { + gpioc@40 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x40 0x20>; bank-name = "C"; }; - gpiod { + gpiod@60 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x60 0x20>; bank-name = "D"; }; - gpioe { + gpioe@80 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0x80 0x20>; bank-name = "E"; }; - gpiof { + gpiof@a0 { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; reg = <0xA0 0x20>; @@ -296,10 +296,10 @@ }; microcode { - update@0 { + update_0 { #include "microcode/m0130673322.dtsi" }; - update@1 { + update_1 { #include "microcode/m0130679901.dtsi" }; }; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index 9c3f2a0..3d81e9d 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -42,7 +42,7 @@ clock-frequency = <1000000000>; }; - pci { + pci@0 { compatible = "pci-x86"; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 5d601b3..931c258 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -53,7 +53,7 @@ clock-frequency = <1000000000>; }; - pci { + pci@0 { compatible = "pci-x86"; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/x86/dts/rtc.dtsi b/arch/x86/dts/rtc.dtsi index 1797e04..9b09d7e 100644 --- a/arch/x86/dts/rtc.dtsi +++ b/arch/x86/dts/rtc.dtsi @@ -1,5 +1,5 @@ / { - rtc { + rtc@70 { compatible = "motorola,mc146818"; u-boot,dm-pre-reloc; reg = <0x70 2>; diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi index 54c3faf..02be132 100644 --- a/arch/x86/dts/serial.dtsi +++ b/arch/x86/dts/serial.dtsi @@ -1,5 +1,5 @@ / { - serial: serial { + serial: serial@3f8 { compatible = "ns16550"; reg = <0x3f8 8>; reg-shift = <0>; diff --git a/arch/x86/dts/skeleton.dtsi b/arch/x86/dts/skeleton.dtsi index b41d241..a20da0a 100644 --- a/arch/x86/dts/skeleton.dtsi +++ b/arch/x86/dts/skeleton.dtsi @@ -9,5 +9,5 @@ #size-cells = <1>; chosen { }; aliases { }; - memory { device_type = "memory"; reg = <0 0>; }; + memory@0 { device_type = "memory"; reg = <0 0>; }; }; diff --git a/doc/device-tree-bindings/pmic/sandbox.txt b/doc/device-tree-bindings/pmic/sandbox.txt index d84c977..c1bef4c 100644 --- a/doc/device-tree-bindings/pmic/sandbox.txt +++ b/doc/device-tree-bindings/pmic/sandbox.txt @@ -24,7 +24,7 @@ Optional subnodes: Example: -sandbox_pmic { +sandbox_pmic@40 { compatible = "sandbox,pmic"; reg = <0x40>; diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index e3229ef..e3e2835 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -1038,11 +1038,11 @@ int cros_ec_decode_ec_flash(const void *blob, int node, const char *name = fdt_get_name(blob, node, NULL); enum ec_flash_region region; - if (0 == strcmp(name, "ro")) { + if (0 == strcmp(name, "ro@0")) { region = EC_FLASH_REGION_RO; - } else if (0 == strcmp(name, "rw")) { + } else if (0 == strcmp(name, "rw@10000")) { region = EC_FLASH_REGION_RW; - } else if (0 == strcmp(name, "wp-ro")) { + } else if (0 == strcmp(name, "wp-ro@f000")) { region = EC_FLASH_REGION_WP_RO; } else { debug("Unknown EC flash region name '%s'\n", name); diff --git a/include/sandbox-adc.h b/include/sandbox-adc.h index 79ff01c..bfc9ce8 100644 --- a/include/sandbox-adc.h +++ b/include/sandbox-adc.h @@ -8,7 +8,7 @@ #ifndef _SANDBOX_ADC_H_ #define _SANDBOX_ADC_H_ -#define SANDBOX_ADC_DEVNAME "adc@0" +#define SANDBOX_ADC_DEVNAME "adc" #define SANDBOX_ADC_DATA_MASK 0xffff /* 16-bits resolution */ #define SANDBOX_ADC_CHANNELS 4 #define SANDBOX_ADC_CHANNEL0_DATA 0x0 diff --git a/test/dm/bus.c b/test/dm/bus.c index 3b5a23b..9e97629 100644 --- a/test/dm/bus.c +++ b/test/dm/bus.c @@ -156,9 +156,9 @@ static int dm_test_bus_children_funcs(struct unit_test_state *uts) ut_asserteq(-ENODEV, device_get_child_by_seq(bus, 2, &dev)); /* Looking for something that is not a child */ - node = fdt_path_offset(blob, "/junk"); + node = fdt_path_offset(blob, "/junk@1"); ut_asserteq(-ENODEV, device_find_child_by_of_offset(bus, node, &dev)); - node = fdt_path_offset(blob, "/d-test"); + node = fdt_path_offset(blob, "/d-test@3"); ut_asserteq(-ENODEV, device_find_child_by_of_offset(bus, node, &dev)); /* Find a valid child */ diff --git a/test/dm/eth.c b/test/dm/eth.c index 6288ae2..ec68a54 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -171,9 +171,9 @@ static int _dm_test_eth_rotate2(struct unit_test_state *uts) ut_asserteq_str("eth@10004000", getenv("ethact")); /* Make sure we can handle device name which is not eth# */ - setenv("ethact", "sbe5"); + setenv("ethact", "sbe5@10005000"); ut_assertok(net_loop(PING)); - ut_asserteq_str("sbe5", getenv("ethact")); + ut_asserteq_str("sbe5@10005000", getenv("ethact")); return 0; } diff --git a/test/dm/gpio.c b/test/dm/gpio.c index 727db18..437fc27 100644 --- a/test/dm/gpio.c +++ b/test/dm/gpio.c @@ -183,7 +183,7 @@ static int dm_test_gpio_phandles(struct unit_test_state *uts) struct udevice *dev, *gpio_a, *gpio_b; ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 0, &dev)); - ut_asserteq_str("a-test", dev->name); + ut_asserteq_str("a-test@0", dev->name); ut_assertok(gpio_request_by_name(dev, "test-gpios", 1, &desc, 0)); ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio_a)); diff --git a/test/dm/pmic.c b/test/dm/pmic.c index 422ea3e..bd652c6 100644 --- a/test/dm/pmic.c +++ b/test/dm/pmic.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Test PMIC get method */ static int dm_test_power_pmic_get(struct unit_test_state *uts) { - const char *name = "sandbox_pmic"; + const char *name = "sandbox_pmic@40"; struct udevice *dev; ut_assertok(pmic_get(name, &dev)); @@ -42,7 +42,7 @@ DM_TEST(dm_test_power_pmic_get, DM_TESTF_SCAN_FDT); /* Test PMIC I/O */ static int dm_test_power_pmic_io(struct unit_test_state *uts) { - const char *name = "sandbox_pmic"; + const char *name = "sandbox_pmic@40"; uint8_t out_buffer, in_buffer; struct udevice *dev; int reg_count, i; diff --git a/test/dm/spmi.c b/test/dm/spmi.c index d519a90..f5693e8 100644 --- a/test/dm/spmi.c +++ b/test/dm/spmi.c @@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Test if bus childs got probed propperly*/ static int dm_test_spmi_probe(struct unit_test_state *uts) { - const char *name = "spmi@0"; + const char *name = "spmi0"; struct udevice *bus, *dev; ut_assertok(uclass_get_device(UCLASS_SPMI, 0, &bus)); diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 49a36cb..32a2b1d 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -190,10 +190,10 @@ static int dm_test_fdt_uclass_seq(struct unit_test_state *uts) /* A few basic santiy tests */ ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_FDT, 3, true, &dev)); - ut_asserteq_str("b-test", dev->name); + ut_asserteq_str("b-test@3", dev->name); ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_FDT, 8, true, &dev)); - ut_asserteq_str("a-test", dev->name); + ut_asserteq_str("a-test@0", dev->name); ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 5, true, &dev)); @@ -201,7 +201,7 @@ static int dm_test_fdt_uclass_seq(struct unit_test_state *uts) /* Test aliases */ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 6, &dev)); - ut_asserteq_str("e-test", dev->name); + ut_asserteq_str("e-test@3", dev->name); ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_TEST_FDT, 7, true, &dev)); @@ -211,18 +211,18 @@ static int dm_test_fdt_uclass_seq(struct unit_test_state *uts) * node */ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 3, &dev)); - ut_asserteq_str("b-test", dev->name); + ut_asserteq_str("b-test@3", dev->name); /* * d-test wants sequence number 3 also, but it can't have it because * b-test gets it first. */ ut_assertok(uclass_get_device(UCLASS_TEST_FDT, 2, &dev)); - ut_asserteq_str("d-test", dev->name); + ut_asserteq_str("d-test@3", dev->name); /* d-test actually gets 0 */ ut_assertok(uclass_get_device_by_seq(UCLASS_TEST_FDT, 0, &dev)); - ut_asserteq_str("d-test", dev->name); + ut_asserteq_str("d-test@3", dev->name); /* initially no one wants seq 1 */ ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_TEST_FDT, 1, @@ -245,11 +245,11 @@ static int dm_test_fdt_offset(struct unit_test_state *uts) struct udevice *dev; int node; - node = fdt_path_offset(blob, "/e-test"); + node = fdt_path_offset(blob, "/e-test@3"); ut_assert(node > 0); ut_assertok(uclass_get_device_by_of_offset(UCLASS_TEST_FDT, node, &dev)); - ut_asserteq_str("e-test", dev->name); + ut_asserteq_str("e-test@3", dev->name); /* This node should not be bound */ node = fdt_path_offset(blob, "/junk");