From patchwork Wed Apr 13 10:52:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Raghavendra, Vignesh" X-Patchwork-Id: 609955 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3qlLJC2W1sz9t49 for ; Wed, 13 Apr 2016 20:53:31 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7F0BDA7689; Wed, 13 Apr 2016 12:53:24 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cvCGvIgkKfI6; Wed, 13 Apr 2016 12:53:24 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6F8EFA768D; Wed, 13 Apr 2016 12:53:17 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 83F20A75FB for ; Wed, 13 Apr 2016 12:53:07 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4mj4a_csFl7q for ; Wed, 13 Apr 2016 12:53:07 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 17304A7519 for ; Wed, 13 Apr 2016 12:53:03 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u3DAqswM029306; Wed, 13 Apr 2016 05:52:54 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u3DAqslB015799; Wed, 13 Apr 2016 05:52:54 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Wed, 13 Apr 2016 05:52:53 -0500 Received: from uda0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u3DAqmgK014166; Wed, 13 Apr 2016 05:52:52 -0500 From: Vignesh R To: Jagan Teki , Tom Rini Date: Wed, 13 Apr 2016 16:22:45 +0530 Message-ID: <1460544768-32750-2-git-send-email-vigneshr@ti.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1460544768-32750-1-git-send-email-vigneshr@ti.com> References: <1460544768-32750-1-git-send-email-vigneshr@ti.com> MIME-Version: 1.0 Cc: Marek Vasut , u-boot@lists.denx.de, Stefan Roese , Chin Liang See Subject: [U-Boot] [PATCH 1/4] spi: cadence_qspi_apb: Support 32 bit AHB address X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" AHB address can be as long as 32 bit, hence remove the CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT and read as u32 value, it anyway does not make sense to mask upper bits. Signed-off-by: Vignesh R Tested-by: Marek Vasut Acked-by: Marek Vasut --- drivers/spi/cadence_qspi_apb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7786dd65f509..a31b43b0114d 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -44,7 +44,6 @@ #define CQSPI_INST_TYPE_QUAD (2) #define CQSPI_STIG_DATA_LEN_MAX (8) -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF) #define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4) @@ -694,7 +693,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, addr_bytes = cmdlen - 1; /* Setup the indirect trigger address */ - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ @@ -791,7 +790,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, return -EINVAL; } /* Setup the indirect trigger address */ - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */