From patchwork Thu Feb 25 15:52:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 588157 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1080814032B for ; Fri, 26 Feb 2016 02:52:40 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 91779A7695; Thu, 25 Feb 2016 16:52:35 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 82sPf-oZdoIY; Thu, 25 Feb 2016 16:52:35 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AB09FA76B1; Thu, 25 Feb 2016 16:52:30 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AE567A7602 for ; Thu, 25 Feb 2016 16:52:23 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jWTPSyuxfwyI for ; Thu, 25 Feb 2016 16:52:23 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 2B615A75E6 for ; Thu, 25 Feb 2016 16:52:19 +0100 (CET) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id u1PFqH6b018004; Thu, 25 Feb 2016 09:52:17 -0600 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1PFqHmE029054; Thu, 25 Feb 2016 09:52:17 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Thu, 25 Feb 2016 09:52:16 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1PFqHLQ002000; Thu, 25 Feb 2016 09:52:17 -0600 From: Nishanth Menon To: Tom Rini Date: Thu, 25 Feb 2016 09:52:11 -0600 Message-ID: <1456415535-22689-3-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1456415535-22689-1-git-send-email-nm@ti.com> References: <1456415535-22689-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Suman Anna Subject: [U-Boot] [PATCH 2/6] ARM: keystone2: K2G: power-off DSP during boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Suman Anna The DSPs are powered on by default upon a Power ON reset, and they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E during the boot in u-boot. This is not functional on K2G though. Extend the existing DSP power-off support to the only DSP present on K2G. Do note that the PSC clock domain module id for DSP on K2G differs from that of previous Keystone2 SoCs. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Tom Rini --- arch/arm/mach-keystone/include/mach/hardware-k2g.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h index fa4162fe9964..ca2a119d3901 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -10,7 +10,7 @@ #ifndef __ASM_ARCH_HARDWARE_K2G_H #define __ASM_ARCH_HARDWARE_K2G_H -#define KS2_NUM_DSPS 0 +#define KS2_NUM_DSPS 1 /* Power and Sleep Controller (PSC) Domains */ #define KS2_LPSC_ALWAYSON 0 @@ -30,7 +30,10 @@ #define KS2_LPSC_MCASP 15 #define KS2_LPSC_SR 16 #define KS2_LPSC_MSMC 17 -#define KS2_LPSC_GEM 18 +#ifdef KS2_LPSC_GEM_0 +#undef KS2_LPSC_GEM_0 +#endif +#define KS2_LPSC_GEM_0 18 #define KS2_LPSC_ARM 19 #define KS2_LPSC_ASRC 20 #define KS2_LPSC_ICSS 21