From patchwork Mon Jan 4 13:12:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 562381 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 744811402D6 for ; Tue, 5 Jan 2016 00:15:21 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Iao1ahLe; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 994864B867; Mon, 4 Jan 2016 14:15:19 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2sram7e0thzG; Mon, 4 Jan 2016 14:15:19 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 20EEB4B859; Mon, 4 Jan 2016 14:15:19 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C2DCC4B859 for ; Mon, 4 Jan 2016 14:15:16 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3VJ6uYZGDQa5 for ; Mon, 4 Jan 2016 14:15:16 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f179.google.com (mail-pf0-f179.google.com [209.85.192.179]) by theia.denx.de (Postfix) with ESMTPS id 40AE84B83E for ; Mon, 4 Jan 2016 14:15:13 +0100 (CET) Received: by mail-pf0-f179.google.com with SMTP id e65so149355484pfe.1 for ; Mon, 04 Jan 2016 05:15:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=oouyCkjmFPy1igsNrQ837F/KrYLWtl6ThEg9I+q95qk=; b=Iao1ahLekZamWD0vJifFdzvEVB/43zwxbjXua0ls7g45jSR/wEUJxdZGEFCX2CIpIC OcF3fqVjzk+d3sp9V97pYwa3OGooQZqvuf9Oh/zqdnrZUCkmzt/LRGxSS9rDh2p9m7PA 7u1/QmRw7dqH3QFuvHlzvgmS3Qp20wCOqbloK5PfcAIq9+VOyam7WSUTZN5FrGjV8yys 5I1EeHWmamgGM09Ep3BUwWK69mxTvOxKzMzPpd5Mk3NcEulsO2vN7OeaYGDGnYXUZKq9 dJkMABfDYj3fSK3CA51MixgGz97anCGeH64KkvY8ElNM4xDzhx9A/yhk6ePtG1zJjl6V BAiw== X-Received: by 10.98.43.204 with SMTP id r195mr56767279pfr.8.1451913311873; Mon, 04 Jan 2016 05:15:11 -0800 (PST) Received: from linux-7smt.suse (gate-zmy3.freescale.com. [192.88.167.1]) by smtp.gmail.com with ESMTPSA id v25sm51820487pfa.77.2016.01.04.05.15.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 04 Jan 2016 05:15:11 -0800 (PST) From: Peng Fan X-Google-Original-From: Peng Fan To: u-boot@lists.denx.de Date: Mon, 4 Jan 2016 21:12:22 +0800 Message-Id: <1451913142-13538-1-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.6.2 Cc: Fabio Estevam Subject: [U-Boot] [PATCH V3] imx: mx7: fix the temperature checking for Rev1.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To TO1.0, we can not rely on finish bit to read temperature. But to TO1.1, the issue was fixed by IC, we can rely on finish bit for temperature reading for TO1.1. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Tim Harvey Cc: Fabio Estevam Cc: Adrian Alonso --- Changes V3: Fix build warning. Changes V2: Discard reading register each time in the while loop for TO1.0. No need to do this. Discard udelay for TO1.1 when reading register. drivers/thermal/imx_thermal.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 09a3c52..6578271 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -130,7 +130,7 @@ static int read_cpu_temperature(struct udevice *dev) #elif defined(CONFIG_MX7) static int read_cpu_temperature(struct udevice *dev) { - unsigned int reg, tmp, start; + unsigned int reg, tmp; unsigned int raw_25c, te1; int temperature; unsigned int *priv = dev_get_priv(dev); @@ -169,18 +169,25 @@ static int read_cpu_temperature(struct udevice *dev) writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set); - start = get_timer(0); - /* Wait max 100ms */ - do { + if (soc_rev() >= CHIP_REV_1_1) { + while ((readl(&ccm_anatop->tempsense1) & + TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0) + ; + reg = readl(&ccm_anatop->tempsense1); + tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; + } else { /* - * Since we can not rely on finish bit, use 1ms delay to get - * temperature. From RM, 17us is enough to get data, but - * to gurantee to get the data, delay 100ms here. + * Since we can not rely on finish bit, use 10ms + * delay to get temperature. From RM, 17us is + * enough to get data, but to gurantee to get + * the data, delay 10ms here. */ + udelay(10000); reg = readl(&ccm_anatop->tempsense1); tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; - } while (get_timer(0) < (start + 100)); + } writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);