From patchwork Thu Dec 31 08:53:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 561857 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 56539140BC8 for ; Thu, 31 Dec 2015 19:51:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=FU5dCbLw; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5BB584B6BE; Thu, 31 Dec 2015 09:50:59 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id F7TkKUJsLiU6; Thu, 31 Dec 2015 09:50:59 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 576E84BAD0; Thu, 31 Dec 2015 09:50:58 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BCB9A4BAB2 for ; Thu, 31 Dec 2015 09:50:24 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gMgshXWcbL6E for ; Thu, 31 Dec 2015 09:50:24 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pf0-f172.google.com (mail-pf0-f172.google.com [209.85.192.172]) by theia.denx.de (Postfix) with ESMTPS id 1CF0D4BAC1 for ; Thu, 31 Dec 2015 09:50:14 +0100 (CET) Received: by mail-pf0-f172.google.com with SMTP id e65so100848520pfe.1 for ; Thu, 31 Dec 2015 00:50:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=IXdXYLSot9nnCVNhtUmIan3BNrD6+sa00e+Na+sOMTc=; b=FU5dCbLw1R/mHpetpIS1sRHYc8FBpy8SmuYR8Wbz2Z4ycovRtJ5N77rX4vn2jQl2wH BpwgEsr+7NFT9nJ5EvRDMYqM1/tEWF30cwYudnPTFo5cIv13NA1vfn2nTs4+T9syG8Dv HmumNUHoTEjt/Uv+TzHeGMZ29kkrV2l3all2wkAUv7Qq3MJRs2JQAC7vazTBouo//Huq GUpIGVK2DiZ64Wps+zaqdtRgu6y1CmNhlElFpeHj/Z0OIN5577mIvT26W3Ac0D9kF4aQ 8UNXMK9PlwJqcB+KlWh4LL15floqXd3sfNIRo2zSYKk01ZVYsS/NTR5VTsLTDAPkhalS bzGw== X-Received: by 10.98.86.195 with SMTP id h64mr100141116pfj.96.1451551813478; Thu, 31 Dec 2015 00:50:13 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id v11sm47310711pfa.81.2015.12.31.00.50.12 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 31 Dec 2015 00:50:13 -0800 (PST) From: Bin Meng To: Simon Glass , York Sun , Alison Wang , U-Boot Mailing List Date: Thu, 31 Dec 2015 00:53:08 -0800 Message-Id: <1451551990-32165-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1451551990-32165-1-git-send-email-bmeng.cn@gmail.com> References: <1451551990-32165-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 6/8] serial: lpuart: Prepare the driver for DM conversion X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Create internal routines which take lpuart's register base as a parameter, in preparation for driver model conversion. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- drivers/serial/serial_lpuart.c | 146 +++++++++++++++++++++++++++-------------- 1 file changed, 95 insertions(+), 51 deletions(-) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 0c0ab87..fed83a6 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -50,46 +50,43 @@ DECLARE_GLOBAL_DATA_PTR; struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE; #ifndef CONFIG_LPUART_32B_REG -static void lpuart_serial_setbrg(void) +static void _lpuart_serial_setbrg(struct lpuart_fsl *reg, int baudrate) { u32 clk = mxc_get_clock(MXC_UART_CLK); u16 sbr; - if (!gd->baudrate) - gd->baudrate = CONFIG_BAUDRATE; - - sbr = (u16)(clk / (16 * gd->baudrate)); + sbr = (u16)(clk / (16 * baudrate)); /* place adjustment later - n/32 BRFA */ - __raw_writeb(sbr >> 8, &base->ubdh); - __raw_writeb(sbr & 0xff, &base->ubdl); + __raw_writeb(sbr >> 8, ®->ubdh); + __raw_writeb(sbr & 0xff, ®->ubdl); } -static int lpuart_serial_getc(void) +static int _lpuart_serial_getc(struct lpuart_fsl *reg) { - while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) + while (!(__raw_readb(®->us1) & (US1_RDRF | US1_OR))) WATCHDOG_RESET(); barrier(); - return __raw_readb(&base->ud); + return __raw_readb(®->ud); } -static void lpuart_serial_putc(const char c) +static void _lpuart_serial_putc(struct lpuart_fsl *reg, const char c) { if (c == '\n') - lpuart_serial_putc('\r'); + _lpuart_serial_putc(reg, '\r'); - while (!(__raw_readb(&base->us1) & US1_TDRE)) + while (!(__raw_readb(®->us1) & US1_TDRE)) WATCHDOG_RESET(); - __raw_writeb(c, &base->ud); + __raw_writeb(c, ®->ud); } /* Test whether a character is in the RX buffer */ -static int lpuart_serial_tstc(void) +static int _lpuart_serial_tstc(struct lpuart_fsl *reg) { - if (__raw_readb(&base->urcfifo) == 0) + if (__raw_readb(®->urcfifo) == 0) return 0; return 1; @@ -99,32 +96,57 @@ static int lpuart_serial_tstc(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static int lpuart_serial_init(void) +static int _lpuart_serial_init(struct lpuart_fsl *reg) { u8 ctrl; - ctrl = __raw_readb(&base->uc2); + ctrl = __raw_readb(®->uc2); ctrl &= ~UC2_RE; ctrl &= ~UC2_TE; - __raw_writeb(ctrl, &base->uc2); + __raw_writeb(ctrl, ®->uc2); - __raw_writeb(0, &base->umodem); - __raw_writeb(0, &base->uc1); + __raw_writeb(0, ®->umodem); + __raw_writeb(0, ®->uc1); /* Disable FIFO and flush buffer */ - __raw_writeb(0x0, &base->upfifo); - __raw_writeb(0x0, &base->utwfifo); - __raw_writeb(0x1, &base->urwfifo); - __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo); + __raw_writeb(0x0, ®->upfifo); + __raw_writeb(0x0, ®->utwfifo); + __raw_writeb(0x1, ®->urwfifo); + __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, ®->ucfifo); /* provide data bits, parity, stop bit, etc */ - lpuart_serial_setbrg(); + _lpuart_serial_setbrg(reg, gd->baudrate); - __raw_writeb(UC2_RE | UC2_TE, &base->uc2); + __raw_writeb(UC2_RE | UC2_TE, ®->uc2); return 0; } +static void lpuart_serial_setbrg(void) +{ + _lpuart_serial_setbrg(base, gd->baudrate); +} + +static int lpuart_serial_getc(void) +{ + return _lpuart_serial_getc(base); +} + +static void lpuart_serial_putc(const char c) +{ + _lpuart_serial_putc(base, c); +} + +static int lpuart_serial_tstc(void) +{ + return _lpuart_serial_tstc(); +} + +static int lpuart_serial_init(void) +{ + return _lpuart_serial_init(base); +} + static struct serial_device lpuart_serial_drv = { .name = "lpuart_serial", .start = lpuart_serial_init, @@ -136,47 +158,44 @@ static struct serial_device lpuart_serial_drv = { .tstc = lpuart_serial_tstc, }; #else -static void lpuart32_serial_setbrg(void) +static void _lpuart32_serial_setbrg(struct lpuart_fsl *reg, int baudrate) { u32 clk = CONFIG_SYS_CLK_FREQ; u32 sbr; - if (!gd->baudrate) - gd->baudrate = CONFIG_BAUDRATE; - - sbr = (clk / (16 * gd->baudrate)); + sbr = (clk / (16 * baudrate)); /* place adjustment later - n/32 BRFA */ - out_be32(&base->baud, sbr); + out_be32(®->baud, sbr); } -static int lpuart32_serial_getc(void) +static int _lpuart32_serial_getc(struct lpuart_fsl *reg) { u32 stat; - while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) { - out_be32(&base->stat, STAT_FLAGS); + while (((stat = in_be32(®->stat)) & STAT_RDRF) == 0) { + out_be32(®->stat, STAT_FLAGS); WATCHDOG_RESET(); } - return in_be32(&base->data) & 0x3ff; + return in_be32(®->data) & 0x3ff; } -static void lpuart32_serial_putc(const char c) +static void _lpuart32_serial_putc(struct lpuart_fsl *reg, const char c) { if (c == '\n') - lpuart32_serial_putc('\r'); + _lpuart32_serial_putc(reg, '\r'); - while (!(in_be32(&base->stat) & STAT_TDRE)) + while (!(in_be32(®->stat) & STAT_TDRE)) WATCHDOG_RESET(); - out_be32(&base->data, c); + out_be32(®->data, c); } /* Test whether a character is in the RX buffer */ -static int lpuart32_serial_tstc(void) +static int _lpuart32_serial_tstc(struct lpuart_fsl *reg) { - if ((in_be32(&base->water) >> 24) == 0) + if ((in_be32(®->water) >> 24) == 0) return 0; return 1; @@ -186,28 +205,53 @@ static int lpuart32_serial_tstc(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static int lpuart32_serial_init(void) +static int _lpuart32_serial_init(struct lpuart_fsl *reg) { u8 ctrl; - ctrl = in_be32(&base->ctrl); + ctrl = in_be32(®->ctrl); ctrl &= ~CTRL_RE; ctrl &= ~CTRL_TE; - out_be32(&base->ctrl, ctrl); + out_be32(®->ctrl, ctrl); - out_be32(&base->modir, 0); - out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE)); + out_be32(®->modir, 0); + out_be32(®->fifo, ~(FIFO_TXFE | FIFO_RXFE)); - out_be32(&base->match, 0); + out_be32(®->match, 0); /* provide data bits, parity, stop bit, etc */ - lpuart32_serial_setbrg(); + _lpuart32_serial_setbrg(reg, gd->baudrate); - out_be32(&base->ctrl, CTRL_RE | CTRL_TE); + out_be32(®->ctrl, CTRL_RE | CTRL_TE); return 0; } +static void lpuart32_serial_setbrg(void) +{ + _lpuart32_serial_setbrg(base, gd->baudrate); +} + +static int lpuart32_serial_getc(void) +{ + return _lpuart32_serial_getc(base); +} + +static void lpuart32_serial_putc(const char c) +{ + _lpuart32_serial_putc(base, c); +} + +static int lpuart32_serial_tstc(void) +{ + return _lpuart32_serial_tstc(base); +} + +static int lpuart32_serial_init(void) +{ + return _lpuart32_serial_init(base); +} + static struct serial_device lpuart32_serial_drv = { .name = "lpuart32_serial", .start = lpuart32_serial_init,