From patchwork Tue Dec 22 09:03:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 559929 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 91D4C140BA1 for ; Tue, 22 Dec 2015 20:04:25 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=xsly91ro; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 605094B79B; Tue, 22 Dec 2015 10:04:21 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IdqlXx0wf414; Tue, 22 Dec 2015 10:04:21 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9A0094B72D; Tue, 22 Dec 2015 10:04:20 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7F4B14B72D for ; Tue, 22 Dec 2015 10:04:16 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7-tHRWSprIDN for ; Tue, 22 Dec 2015 10:04:16 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f50.google.com (mail-pa0-f50.google.com [209.85.220.50]) by theia.denx.de (Postfix) with ESMTPS id 07FE04B71E for ; Tue, 22 Dec 2015 10:04:13 +0100 (CET) Received: by mail-pa0-f50.google.com with SMTP id cy9so32044574pac.0 for ; Tue, 22 Dec 2015 01:04:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=MYNGn8Pw4ZKHcISuQ+035oBLThsyAHC5z6VSTYXOF1U=; b=xsly91rok5udgMCDwgeNK1CCtMORIQ92Mhr3tCas/dDnGi1wmikltJalYqujtjNG6z 7bM4wZSlIQglPYiBoq6nKpQAg2/YO6SUsKCSJ95sEOttUvTB7PSC6MtfRUYUk1nCX3l4 aUUnDHXfCX9xSwo/q9N2tI6JLucIEvZT8TZ1rugrS4UsxENB1nkpHB5KFTZlWkN8uao3 sWYyWkdRptwuNPYlmInnnC9PPwhAo51QZDrz2o55EefBAgzaTouOSZuOFrD5LybRweO5 KUzqrSa9xdCyR4HeenqUpaRG/6ttvngsZXedk5jeB1XJVNliLr0VHXk3jspOWkHMsthg 2+LA== X-Received: by 10.66.254.39 with SMTP id af7mr34136525pad.43.1450775051433; Tue, 22 Dec 2015 01:04:11 -0800 (PST) Received: from linux-7smt.suse (gate-zmy3.freescale.com. [192.88.167.1]) by smtp.gmail.com with ESMTPSA id yl1sm44407476pac.35.2015.12.22.01.04.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Dec 2015 01:04:10 -0800 (PST) From: Peng Fan To: u-boot@lists.denx.de Date: Tue, 22 Dec 2015 17:03:55 +0800 Message-Id: <1450775035-2339-1-git-send-email-van.freenix@gmail.com> X-Mailer: git-send-email 2.6.2 Subject: [U-Boot] [PATCH] imx: mx6sxsabresd: support emmc X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Peng Fan For i.MX6SX SABRESD, USDHC4 can be used for SD and EMMC, default it is used for SD. This patch introduces EMMC pinmux settings and a new macro CONFIG_MX6SXSABRESD_EMMC_REWORK. If the board has been reworked to support emmc, need to enable this macro. Signed-off-by: Peng Fan Cc: Stefano Babic --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 78f0151..6168b26 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -109,6 +109,20 @@ static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc4_emmc_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const fec1_pads[] = { MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -302,7 +316,11 @@ int board_early_init_f(void) static struct fsl_esdhc_cfg usdhc_cfg[3] = { {USDHC2_BASE_ADDR, 0, 4}, {USDHC3_BASE_ADDR}, +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK + {USDHC4_BASE_ADDR, 0, 8}, +#else {USDHC4_BASE_ADDR}, +#endif }; #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) @@ -327,7 +345,11 @@ int board_mmc_getcd(struct mmc *mmc) ret = !gpio_get_value(USDHC3_CD_GPIO); break; case USDHC4_BASE_ADDR: +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK + ret = 1; +#else ret = !gpio_get_value(USDHC4_CD_GPIO); +#endif break; } @@ -361,9 +383,14 @@ int board_mmc_init(bd_t *bis) usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; case 2: +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK + imx_iomux_v3_setup_multiple_pads( + usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads)); +#else imx_iomux_v3_setup_multiple_pads( usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); gpio_direction_input(USDHC4_CD_GPIO); +#endif usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); break; default: @@ -410,9 +437,14 @@ int board_mmc_init(bd_t *bis) usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; break; case 3: +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK + imx_iomux_v3_setup_multiple_pads( + usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads)); +#else imx_iomux_v3_setup_multiple_pads( usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); gpio_direction_input(USDHC4_CD_GPIO); +#endif usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; break;