From patchwork Wed Dec 16 01:42:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 557274 X-Patchwork-Delegate: yamada.m@jp.panasonic.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 48C181402BF for ; Wed, 16 Dec 2015 12:43:26 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F12D84BD10; Wed, 16 Dec 2015 02:43:24 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uYpf_X9aPOBz; Wed, 16 Dec 2015 02:43:24 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 79C204BD06; Wed, 16 Dec 2015 02:43:24 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 14AFB4BD09 for ; Wed, 16 Dec 2015 02:43:08 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ig-XpRP_YVHl for ; Wed, 16 Dec 2015 02:43:08 +0100 (CET) X-policyd-weight: SBL_XBL_SPAMHAUS=ERR(-1.5) SPAMCOP=SKIP(-1.5) BL_NJABL=SKIP(-1.5) DSBL_ORG=ERR(0) (only DNSBL check requested) Received: from conuserg012-v.nifty.com (unknown [202.248.44.38]) by theia.denx.de (Postfix) with ESMTPS id 123994BD02 for ; Wed, 16 Dec 2015 02:42:54 +0100 (CET) Received: from beagle.diag.org (p14090-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.90]) (authenticated) by conuserg012-v.nifty.com with ESMTP id tBG1gIbb023142; Wed, 16 Dec 2015 10:42:18 +0900 X-Nifty-SrcIP: [153.142.97.90] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 16 Dec 2015 10:42:29 +0900 Message-Id: <1450230149-11545-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Subject: [U-Boot] [PATCH] ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_* X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The bit 27-24 of the DTCR register is described as RANKEN in the DDR PHY databook. Follow this abbreviation. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/ddrphy/ddrphy-training.c | 4 ++-- arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c index f1a2341..b4d369a 100644 --- a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c +++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c @@ -32,8 +32,8 @@ void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) /* Use Multi-Purpose Register for DQS gate training */ tmp |= DTCR_DTMPR; /* Specify the rank enabled for data-training */ - tmp &= ~DTCR_RNKEN_MASK; - tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK; + tmp &= ~DTCR_RANKEN_MASK; + tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK; writel(tmp, p); } diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index adcc972..0c3b508 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -147,8 +147,8 @@ struct ddrphy { #define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ #define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT)) #define DTCR_DTMPR (1 << 6) /* Data Training using MPR */ -#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */ -#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT)) +#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */ +#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT)) #define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ #define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))