diff mbox

[U-Boot,v3,1/2] mmc: socfpga_dw_mmc: Move drvsel and smplsel to dts

Message ID 1448502223-3159-1-git-send-email-clsee@altera.com
State Superseded
Delegated to: Marek Vasut
Headers show

Commit Message

Chin Liang See Nov. 26, 2015, 1:43 a.m. UTC 
socfpga_dw_mmc driver will obtain the drvsel and
smplsel value from device tree instead of definition
in config header file.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Marek Vasut <marex@denx.de>
---
Changes for v3
- Split patch to separte DTS and driver patches
Changes for v2
- Put default value for drvsel to 3 in case node in DT missing
- Remove unnecessary ad-hoc vairable
- Free up first calloc if second calloc failed
---
 drivers/mmc/socfpga_dw_mmc.c     | 29 +++++++++++++++++++++--------
 include/configs/socfpga_common.h |  2 --
 2 files changed, 21 insertions(+), 10 deletions(-)

Comments

Jaehoon Chung Nov. 26, 2015, 4:36 a.m. UTC | #1 
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

On 11/26/2015 10:43 AM, Chin Liang See wrote:
> socfpga_dw_mmc driver will obtain the drvsel and
> smplsel value from device tree instead of definition
> in config header file.
> 
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> Acked-by: Marek Vasut <marex@denx.de>
> ---
> Changes for v3
> - Split patch to separte DTS and driver patches
> Changes for v2
> - Put default value for drvsel to 3 in case node in DT missing
> - Remove unnecessary ad-hoc vairable
> - Free up first calloc if second calloc failed
> ---
>  drivers/mmc/socfpga_dw_mmc.c     | 29 +++++++++++++++++++++--------
>  include/configs/socfpga_common.h |  2 --
>  2 files changed, 21 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> index 8076761..2bd0ebd 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -19,21 +19,23 @@ static const struct socfpga_clock_manager *clock_manager_base =
>  static const struct socfpga_system_manager *system_manager_base =
>  		(void *)SOCFPGA_SYSMGR_ADDRESS;
>  
> -static void socfpga_dwmci_clksel(struct dwmci_host *host)
> -{
> +/* socfpga implmentation specific drver private data */
> +struct dwmci_socfpga_priv_data {
>  	unsigned int drvsel;
>  	unsigned int smplsel;
> +};
> +
> +static void socfpga_dwmci_clksel(struct dwmci_host *host)
> +{
> +	struct dwmci_socfpga_priv_data *priv = host->priv;
>  
>  	/* Disable SDMMC clock. */
>  	clrbits_le32(&clock_manager_base->per_pll.en,
>  		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
>  
> -	/* Configures drv_sel and smpl_sel */
> -	drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
> -	smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
> -
> -	debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
> -	writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
> +	debug("%s: drvsel %d smplsel %d\n", __func__,
> +	      priv->drvsel, priv->smplsel);
> +	writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
>  		&system_manager_base->sdmmcgrp_ctrl);
>  
>  	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
> @@ -50,6 +52,7 @@ static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
>  	const unsigned long clk = cm_get_mmc_controller_clk_hz();
>  
>  	struct dwmci_host *host;
> +	struct dwmci_socfpga_priv_data *priv;
>  	fdt_addr_t reg_base;
>  	int bus_width, fifo_depth;
>  
> @@ -83,6 +86,13 @@ static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
>  	if (!host)
>  		return -ENOMEM;
>  
> +	/* Allocate the priv */
> +	priv = calloc(1, sizeof(*priv));
> +	if (!priv) {
> +		free(host);
> +		return -ENOMEM;
> +	}
> +
>  	host->name = "SOCFPGA DWMMC";
>  	host->ioaddr = (void *)reg_base;
>  	host->buswidth = bus_width;
> @@ -92,6 +102,9 @@ static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
>  	host->bus_hz = clk;
>  	host->fifoth_val = MSIZE(0x2) |
>  		RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
> +	priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
> +	priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
> +	host->priv = priv;
>  
>  	return add_dwmci(host, host->bus_hz, 400000);
>  }
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index f6808b5..b661cc2 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -153,8 +153,6 @@
>  #define CONFIG_DWMMC
>  #define CONFIG_SOCFPGA_DWMMC
>  #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
> -#define CONFIG_SOCFPGA_DWMMC_DRVSEL	3
> -#define CONFIG_SOCFPGA_DWMMC_SMPSEL	0
>  /* FIXME */
>  /* using smaller max blk cnt to avoid flooding the limited stack we have */
>  #define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
>
Marek Vasut Nov. 26, 2015, 4:27 p.m. UTC | #2 
On Thursday, November 26, 2015 at 02:43:43 AM, Chin Liang See wrote:
> socfpga_dw_mmc driver will obtain the drvsel and
> smplsel value from device tree instead of definition
> in config header file.
> 
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> Acked-by: Marek Vasut <marex@denx.de>

Applied both, thanks!

Best regards,
Marek Vasut
diff mbox

Patch

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 8076761..2bd0ebd 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -19,21 +19,23 @@  static const struct socfpga_clock_manager *clock_manager_base =
 static const struct socfpga_system_manager *system_manager_base =
 		(void *)SOCFPGA_SYSMGR_ADDRESS;
 
-static void socfpga_dwmci_clksel(struct dwmci_host *host)
-{
+/* socfpga implmentation specific drver private data */
+struct dwmci_socfpga_priv_data {
 	unsigned int drvsel;
 	unsigned int smplsel;
+};
+
+static void socfpga_dwmci_clksel(struct dwmci_host *host)
+{
+	struct dwmci_socfpga_priv_data *priv = host->priv;
 
 	/* Disable SDMMC clock. */
 	clrbits_le32(&clock_manager_base->per_pll.en,
 		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 
-	/* Configures drv_sel and smpl_sel */
-	drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
-	smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
-
-	debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
-	writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
+	debug("%s: drvsel %d smplsel %d\n", __func__,
+	      priv->drvsel, priv->smplsel);
+	writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
 		&system_manager_base->sdmmcgrp_ctrl);
 
 	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
@@ -50,6 +52,7 @@  static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
 	const unsigned long clk = cm_get_mmc_controller_clk_hz();
 
 	struct dwmci_host *host;
+	struct dwmci_socfpga_priv_data *priv;
 	fdt_addr_t reg_base;
 	int bus_width, fifo_depth;
 
@@ -83,6 +86,13 @@  static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
 	if (!host)
 		return -ENOMEM;
 
+	/* Allocate the priv */
+	priv = calloc(1, sizeof(*priv));
+	if (!priv) {
+		free(host);
+		return -ENOMEM;
+	}
+
 	host->name = "SOCFPGA DWMMC";
 	host->ioaddr = (void *)reg_base;
 	host->buswidth = bus_width;
@@ -92,6 +102,9 @@  static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
 	host->bus_hz = clk;
 	host->fifoth_val = MSIZE(0x2) |
 		RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+	priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
+	priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
+	host->priv = priv;
 
 	return add_dwmci(host, host->bus_hz, 400000);
 }
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f6808b5..b661cc2 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -153,8 +153,6 @@ 
 #define CONFIG_DWMMC
 #define CONFIG_SOCFPGA_DWMMC
 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL	3
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL	0
 /* FIXME */
 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */