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[U-Boot,PATCHv2] arm: socfpga: enable data/inst prefetch and shared override in the L2

Message ID 1444922016-3501-1-git-send-email-dinguyen@opensource.altera.com
State Accepted
Delegated to: Marek Vasut
Headers show

Commit Message

Dinh Nguyen Oct. 15, 2015, 3:13 p.m. UTC 
From: Dinh Nguyen <dinguyen@opensource.altera.com>

Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: s/PL310_/L310_
---
 arch/arm/include/asm/pl310.h |  2 ++
 arch/arm/mach-socfpga/misc.c | 12 ++++++++++++
 2 files changed, 14 insertions(+)

Comments

Marek Vasut Oct. 17, 2015, 12:15 a.m. UTC | #1 
On Thursday, October 15, 2015 at 05:13:36 PM, dinguyen@opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Update the L2 AUX CTRL settings for the SoCFPGA.
> 
> Enabling D and I prefetch bits helps improve SDRAM performance on the
> platform.
> 
> Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
> PL310 Auxiliary Control register (shared attribute override enable) has the
> side effect of transforming Normal Shared Non-cacheable reads into
> Cacheable no-allocate reads.
> 
> Coherent DMA buffers in Linux always have a Cacheable alias via the
> kernel linear mapping and the processor can speculatively load cache
> lines into the PL310 controller. With bit 22 cleared, Non-cacheable
> reads would unexpectedly hit such cache lines leading to buffer
> corruption.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Applied, thanks!

Best regards,
Marek Vasut
diff mbox

Patch

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index de7650e..d588f94 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -17,6 +17,8 @@ 
 #define L2X0_CTRL_EN				1
 
 #define L310_SHARED_ATT_OVERRIDE_ENABLE		(1 << 22)
+#define L310_AUX_CTRL_DATA_PREFETCH_MASK	(1 << 28)
+#define L310_AUX_CTRL_INST_PREFETCH_MASK	(1 << 29)
 
 struct pl310_regs {
 	u32 pl310_cache_id;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 0940cc5..bbd31ef 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -52,6 +52,18 @@  void enable_caches(void)
 #endif
 }
 
+void v7_outer_cache_enable(void)
+{
+	/* disable the L2 cache */
+	writel(0, &pl310->pl310_ctrl);
+
+	/* enable BRESP, instruction and data prefetch, full line of zeroes */
+	setbits_le32(&pl310->pl310_aux_ctrl,
+		     L310_AUX_CTRL_DATA_PREFETCH_MASK |
+		     L310_AUX_CTRL_INST_PREFETCH_MASK |
+		     L310_SHARED_ATT_OVERRIDE_ENABLE);
+}
+
 /*
  * DesignWare Ethernet initialization
  */