From patchwork Fri Oct 9 13:09:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liviu Dudau X-Patchwork-Id: 528215 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AF839140328 for ; Sat, 10 Oct 2015 00:19:55 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1D27D4B8CF; Fri, 9 Oct 2015 15:19:49 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EA-fLw4e7jns; Fri, 9 Oct 2015 15:19:49 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1D9F64B8CB; Fri, 9 Oct 2015 15:19:42 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7A8164B860 for ; Fri, 9 Oct 2015 15:15:52 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hw5qE7hQMxtI for ; Fri, 9 Oct 2015 15:15:52 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by theia.denx.de (Postfix) with ESMTP id 2BCD94B858 for ; Fri, 9 Oct 2015 15:15:47 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 214DC399; Fri, 9 Oct 2015 06:09:25 -0700 (PDT) Received: from e106497-lin.cambridge.arm.com (e106497-lin.cambridge.arm.com [10.2.131.158]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 04F4E3F687; Fri, 9 Oct 2015 06:09:24 -0700 (PDT) From: Liviu Dudau To: Linus Walleij , David Feng , Ryan Harkin , Tom Rini Date: Fri, 9 Oct 2015 14:09:11 +0100 Message-Id: <1444396152-16295-2-git-send-email-Liviu.Dudau@foss.arm.com> X-Mailer: git-send-email 2.6.0 In-Reply-To: <1444396152-16295-1-git-send-email-Liviu.Dudau@foss.arm.com> References: <1444396152-16295-1-git-send-email-Liviu.Dudau@foss.arm.com> X-Mailman-Approved-At: Fri, 09 Oct 2015 15:19:35 +0200 Cc: U-Boot ML Subject: [U-Boot] [PATCH 1/2] vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel. Declare a secondary memory bank and set the sizes correctly. Signed-off-by: Liviu Dudau Reviewed-by: Linus Walleij --- board/armltd/vexpress64/vexpress64.c | 8 ++++++++ include/configs/vexpress_aemv8a.h | 4 +++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 7cb4e00..6df9d60 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -38,6 +38,14 @@ int dram_init(void) return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + /* * Board specific reset that is system reset. */ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 6107c64..f06344a 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -164,11 +164,13 @@ #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2 (0x880000000) /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE +#define PHYS_SDRAM_2_SIZE 0x180000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Enable memtest */