From patchwork Fri Oct 9 12:11:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Chou X-Patchwork-Id: 528197 X-Patchwork-Delegate: thomas@wytron.com.tw Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CA82E1409B7 for ; Fri, 9 Oct 2015 23:12:07 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 30F474B8B0; Fri, 9 Oct 2015 14:12:06 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yvEafgdfTQlA; Fri, 9 Oct 2015 14:12:05 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7F6564B8BB; Fri, 9 Oct 2015 14:12:05 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9A9B24B8BB for ; Fri, 9 Oct 2015 14:12:02 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UHcKL_-nAmHq for ; Fri, 9 Oct 2015 14:12:02 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from www.wytron.com.tw (220-134-43-68.HINET-IP.hinet.net [220.134.43.68]) by theia.denx.de (Postfix) with ESMTP id 07DE44B8C6 for ; Fri, 9 Oct 2015 14:11:56 +0200 (CEST) Received: from localhost.localdomain (unknown [192.168.1.250]) by www.wytron.com.tw (Postfix) with ESMTP id 2C2F1D00228; Fri, 9 Oct 2015 20:11:53 +0800 (CST) From: Thomas Chou To: u-boot@lists.denx.de Date: Fri, 9 Oct 2015 20:11:48 +0800 Message-Id: <1444392708-31971-1-git-send-email-thomas@wytron.com.tw> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1444119708-6934-1-git-send-email-thomas@wytron.com.tw> References: <1444119708-6934-1-git-send-email-thomas@wytron.com.tw> Cc: Marek Vasut , clsee@altera.com, lftan@altera.com Subject: [U-Boot] [PATCH v2] nios2: set default cache configuration in start.S X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Set default icache and dcache configuration for start.S. We want to remove the CONFIG_SYS_{I,D}CACHE_SIZE... configuration macros. As we are just barely starting from reset, there is no luxury of device tree. We will set some maximum cache configuration so that it will work for most configurations. This is used only in this start.S. The speed penalty is only once here. After start up, during board initialization, cpu information will be extracted from device tree. Then cache flush operations will have correct cache configurations. Signed-off-by: Thomas Chou Acked-by: Marek Vasut --- v2 change commit message. arch/nios2/cpu/start.S | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 17cab6a..8758e7e 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -9,6 +9,15 @@ #include #include +/* + * icache and dcache configuration used only for start.S. + * the values are chosen so that it will work for all configuration. + */ +#define ICACHE_LINE_SIZE 32 /* fixed 32 */ +#define ICACHE_SIZE_MAX 0x10000 /* 64k max */ +#define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */ +#define DCACHE_SIZE_MAX 0x10000 /* 64k max */ + /* RESTART */ .text .global _start, _except_start, _except_end @@ -22,9 +31,9 @@ _start: * just be invalidating the cache a second time. If cache * is not implemented initi behaves as nop. */ - ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE) - movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE) - ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE) + ori r4, r0, %lo(ICACHE_LINE_SIZE) + movhi r5, %hi(ICACHE_SIZE_MAX) + ori r5, r5, %lo(ICACHE_SIZE_MAX) 0: initi r5 sub r5, r5, r4 bgt r5, r0, 0b @@ -51,10 +60,9 @@ _except_end: * DCACHE INIT -- if dcache not implemented, initd behaves as * nop. */ - movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE) - ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE) - movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE) - ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE) + ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN) + movhi r5, %hi(DCACHE_SIZE_MAX) + ori r5, r5, %lo(DCACHE_SIZE_MAX) mov r6, r0 1: initd 0(r6) add r6, r6, r4