diff mbox

[U-Boot] ARM: k2e/l: Apply WA for selecting PA clock source

Message ID 1444284107-6352-1-git-send-email-lokeshvutla@ti.com
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

Lokesh Vutla Oct. 8, 2015, 6:01 a.m. UTC 
On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"

Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/mach-keystone/clock.c              | 10 +++++++---
 arch/arm/mach-keystone/include/mach/clock.h |  1 +
 board/ti/ks2_evm/board.c                    |  4 ++++
 3 files changed, 12 insertions(+), 3 deletions(-)

Comments

Tom Rini Oct. 20, 2015, 12:06 a.m. UTC | #1 
On Thu, Oct 08, 2015 at 11:31:47AM +0530, Lokesh Vutla wrote:

> On keystone2 Lamarr and Edison platforms, the PA clocksource
> mux in PLL REG1, can be changed only after enabling its clock
> domain.
> So selecting the output of PASS PLL as input to PA only after
> enabling the clockdomain.
> This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
> and based on the previous work done by "Hao Zhang <hzhang@ti.com>"
> 
> Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
> Reported-by: Vitaly Andrianov <vitalya@ti.com>
> Tested-by: Vitaly Andrianov <vitalya@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Applied to u-boot/master, thanks!
diff mbox

Patch

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index fc3eadb..6cb6467 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -33,6 +33,11 @@  const struct keystone_pll_regs keystone_pll_regs[] = {
 	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
 };
 
+inline void pll_pa_clk_sel(void)
+{
+	setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK);
+}
+
 static void wait_for_completion(const struct pll_init_data *data)
 {
 	int i;
@@ -180,9 +185,8 @@  void configure_secondary_pll(const struct pll_init_data *data)
 	sdelay(21000);
 
 	/* Select the Output of PASS PLL as input to PASS */
-	if (data->pll == PASS_PLL)
-		setbits_le32(keystone_pll_regs[data->pll].reg1,
-			     CFG_PLLCTL1_PAPLL_MASK);
+	if (data->pll == PASS_PLL && cpu_is_k2hk())
+		pll_pa_clk_sel();
 
 	/* Select the Output of ARM PLL as input to ARM */
 	if (data->pll == TETRIS_PLL)
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index ddc5f8e..7e51702 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -118,6 +118,7 @@  unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 int clk_set_rate(unsigned int clk, unsigned long hz);
 int get_max_dev_speed(void);
 int get_max_arm_speed(void);
+void pll_pa_clk_sel(void);
 
 #endif
 #endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 859a260..bee42bc 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -14,6 +14,7 @@ 
 #include <fdt_support.h>
 #include <asm/arch/ddr3.h>
 #include <asm/arch/psc_defs.h>
+#include <asm/arch/clock.h>
 #include <asm/ti-common/ti-aemif.h>
 #include <asm/ti-common/keystone_net.h>
 
@@ -81,6 +82,9 @@  int board_eth_init(bd_t *bis)
 	if (psc_enable_module(KS2_LPSC_CRYPTO))
 		return -1;
 
+	if (cpu_is_k2e() || cpu_is_k2l())
+		pll_pa_clk_sel();
+
 	port_num = get_num_eth_ports();
 
 	for (j = 0; j < port_num; j++) {