From patchwork Wed Oct 7 20:54:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylvain Rochet X-Patchwork-Id: 527431 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6A391140D89 for ; Thu, 8 Oct 2015 08:55:59 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AA5E54B8B4; Wed, 7 Oct 2015 23:55:55 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qIrj9NBEf5iI; Wed, 7 Oct 2015 23:55:55 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 85DE14B8B7; Wed, 7 Oct 2015 23:55:51 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D53254B895 for ; Wed, 7 Oct 2015 23:36:04 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3s_ZzfZbP7TH for ; Wed, 7 Oct 2015 23:36:04 +0200 (CEST) X-Greylist: delayed 2493 seconds by postgrey-1.34 at theia; Wed, 07 Oct 2015 23:36:00 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from guillaumet.finsecur.com (mx-guillaumet.finsecur.com [91.217.234.131]) by theia.denx.de (Postfix) with ESMTPS id A64684B894 for ; Wed, 7 Oct 2015 23:36:00 +0200 (CEST) Received: from [172.16.8.13] (helo=spice.lan) by guillaumet.finsecur.com with esmtps (TLS1.2:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1ZjvjF-00089E-6O; Wed, 07 Oct 2015 22:54:25 +0200 Received: from gradator by spice.lan with local (Exim 4.86) (envelope-from ) id 1ZjvjE-0006Dz-Tv; Wed, 07 Oct 2015 22:54:25 +0200 From: Sylvain Rochet To: Nicolas Ferre , Ludovic Desroches , Josh Wu , Wenyou Yang , =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= , u-boot@lists.denx.de Date: Wed, 7 Oct 2015 22:54:22 +0200 Message-Id: <1444251262-23862-1-git-send-email-sylvain.rochet@finsecur.com> X-Mailer: git-send-email 2.5.1 X-SA-Exim-Connect-IP: 172.16.8.13 X-SA-Exim-Mail-From: sylvain.rochet@finsecur.com X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on guillaumet.finsecur.com X-Spam-Level: X-Spam-Status: No, score=-2.9 required=5.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.3.2 X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on guillaumet.finsecur.com) X-Mailman-Approved-At: Wed, 07 Oct 2015 23:55:47 +0200 Cc: Sylvain Rochet Subject: [U-Boot] [PATCH] net: phy: micrel: disable NAND-tree for KSZ8051 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" NAND-tree is used to check wiring between MAC and PHY using NAND gates on the PHY side, hence the name. NAND-tree initial status is latched at reset by probing the IRQ pin. However some devices are sharing the PHY IRQ pin with other peripherals such as Atmel SAMA5D[34]x-EK boards when using the optional TM7000 display module, therefore they are switching the PHY in NAND-tree test mode depending on the current IRQ line status at reset. This patch ensure PHY is not in NAND-tree test mode only for the Micrel KSZ8051 PHY used by Atmel. There are other Micrel PHY affected but I doubt they are used on such weird hardware design. Signed-off-by: Sylvain Rochet Acked-by: Joe Hershberger --- drivers/net/phy/micrel.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 507b9a3..a4a0efa 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -22,6 +22,34 @@ static struct phy_driver KSZ804_driver = { .shutdown = &genphy_shutdown, }; +/** + * KSZ8051 + */ +#define MII_KSZ8051_PHY_OMSO 0x16 +#define MII_KSZ8051_PHY_OMSO_NAND_TREE_ON (1 << 5) + +static int ksz8051_config(struct phy_device *phydev) +{ + unsigned val; + + /* Disable NAND-tree */ + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); + val &= ~MII_KSZ8051_PHY_OMSO_NAND_TREE_ON; + phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val); + + return genphy_config(phydev); +} + +static struct phy_driver KSZ8051_driver = { + .name = "Micrel KSZ8051", + .uid = 0x221550, + .mask = 0xfffff0, + .features = PHY_BASIC_FEATURES, + .config = &ksz8051_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + #ifndef CONFIG_PHY_MICREL_KSZ9021 /* * I can't believe Micrel used the exact same part number @@ -215,6 +243,7 @@ static struct phy_driver ksz9031_driver = { int phy_micrel_init(void) { phy_register(&KSZ804_driver); + phy_register(&KSZ8051_driver); #ifdef CONFIG_PHY_MICREL_KSZ9021 phy_register(&ksz9021_driver); #else