From patchwork Wed Sep 16 07:54:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Qiang X-Patchwork-Id: 518644 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7FFEC140134 for ; Thu, 17 Sep 2015 08:50:57 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 225B64B7D1; Thu, 17 Sep 2015 00:50:29 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Harx--wJHHlI; Thu, 17 Sep 2015 00:50:29 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9301F4B714; Thu, 17 Sep 2015 00:50:23 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1C1084B65A for ; Wed, 16 Sep 2015 10:16:25 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Qh334paZSEZ5 for ; Wed, 16 Sep 2015 10:16:21 +0200 (CEST) X-Greylist: delayed 901 seconds by postgrey-1.34 at theia; Wed, 16 Sep 2015 10:16:11 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2on0139.outbound.protection.outlook.com [65.55.169.139]) by theia.denx.de (Postfix) with ESMTPS id 43F434B6C7 for ; Wed, 16 Sep 2015 10:16:10 +0200 (CEST) Received: from CH1PR03CA002.namprd03.prod.outlook.com (10.255.156.147) by BLUPR0301MB1538.namprd03.prod.outlook.com (10.162.213.156) with Microsoft SMTP Server (TLS) id 15.1.268.17; Wed, 16 Sep 2015 08:00:56 +0000 Received: from BL2FFO11FD032.protection.gbl (10.255.156.132) by CH1PR03CA002.outlook.office365.com (10.255.156.147) with Microsoft SMTP Server (TLS) id 15.1.274.16 via Frontend Transport; Wed, 16 Sep 2015 08:00:56 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; freescale.mail.onmicrosoft.com; dmarc=none action=none header.from=freescale.com; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD032.mail.protection.outlook.com (10.173.160.73) with Microsoft SMTP Server (TLS) id 15.1.262.18 via Frontend Transport; Wed, 16 Sep 2015 08:00:56 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t8G80pOX002632; Wed, 16 Sep 2015 01:00:52 -0700 From: Zhao Qiang To: Date: Wed, 16 Sep 2015 15:54:58 +0800 Message-ID: <1442390100-47677-1-git-send-email-qiang.zhao@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BL2FFO11FD032; 1:9l/O+JzjSO5YGTAqmeqFIYfY7VyQaLwLFnPgs+e7eCRY1sW6K01q/gaOXuQlZ1/tbHYYgUxF+gY2gZZV7kVn9DJTqJ6o8mRFIpaCjhj1fva5kH3H7Sk5pFujYkkULy93shgtuaSMb9u4TxIQMHM3fKIKO/wD8DntncAf3yGtCrRfjL2LxhrCZ+kXSZQ/tFD3t2Bnx9AlDg9B3+5tnlnNhA+FQxF/eBq/6WxKcUd+SOQDuy35o3df0dnuIzmoSeKDpKkIJMhYU9LsR9Ot9AMnBYA7J8Mwyq4CbVxcF8eZVyl7rlW39wVB8WUsBdiQHypWr0KsME+XccT7gGXRr/OnrqPA7DzCClgWox05pRT9gMzR3I6bQSuQBveC4YEH7b4uIjHXdEeymiOfFa4tVhxjFw== X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(2980300002)(1109001)(1110001)(339900001)(189002)(199003)(104016003)(48376002)(92566002)(2351001)(33646002)(50986999)(5007970100001)(6806004)(106466001)(19580395003)(5001860100001)(229853001)(19580405001)(77096005)(46102003)(69596002)(85426001)(50466002)(86362001)(5003940100001)(87936001)(11100500001)(68736005)(97736004)(47776003)(36756003)(5001960100002)(64706001)(107886002)(189998001)(110136002)(2371004)(105606002)(50226001)(81156007)(4001540100001)(62966003)(5001830100001)(4001450100002)(77156002)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR0301MB1538; H:az84smr01.freescale.net; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Exchange-Diagnostics: 1; BLUPR0301MB1538; 2:RfAi9P8ZHfbhQF+Ssb7asReNYU9hUzC/7X4srEAvvlszRRDsXvIIxnNTi6hVq83sEIHdqH+JBkqRzanDmLarXVgnRgAnsm2uN+Ui4aObPFrzaGDeFl0KS9K2qPBCrMYi4KLOjs8WSrGXeGGMwdYe0/3Ytt3t2UDqU5SxnZwxEC8=; 3:0WwfJu8Vr1rI3u44yDnf7wwVYatJcHsxYykFI/PqaT2dpTsch+jucvMdRmRn04TGuhDXjUE+lnzlQc97IjDwPPg5crHfFkchwUKhc782d66utmK6uJVA7ckCQeDDjzgWFLvCJkdlafgkNDkBmKafRAIKDuB4h8+ZpD4g5Ur3Vse3f53yfoTtdLRMX8O8POYqz5FMrLsrH5MypA8LI8z2WrshlLgBkihdU+KVc3KEr7I=; 25:K14Qf2owxFTSkXjSZ+KGnyaQ8ykfTBbVoVsSD9EqX1tMzUzdfPg1S4AyorfZUliP1BPpy3WOBEQWavLNJfZvDiPJ3btTgYHUnKRPG87EFTG8sMyVHUDiISDDsaGMnn0I4WQx4UrkzfGiO3oAKu0H4bStie9oroZaRdJfxbPgw2P6cfUYqybmqnInS6MydhBxZXBGH5BHYPHkXUVG0D1esnaRvEj4hL2Ejbc/R62us8hKexXvMaSpEMxYudGanQPCwqexJ9H/jN2k2YLdypuVRA== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR0301MB1538; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0301MB1538; 20:2K79V3g8p5CrfIGDs7eji91A7tlXNxRYar6MPllo66zfenM/jkjyIvrJr9zqCArrEmUbAwblqhJnPtkhQVvj+xyCKIvujJVKcIVilUvMUrCu51g462xUt1VDqrkPW3lXOsburjJeetbQ4Puu+J89Q55PlVnG1X5QfrmFIhqA7xikUdYexC2lvQqyKT2VLKdmbFL4CG0BSdPSR5tiCybKV7WDen6UjOVfonhkjc313S5YuPeIna2Vd9P/w3gk+7enFBR1qYytiyLNzW457o7EIqZR7UjO/odC+zTUvq8FfrAFpO16kOsIOKeRDKtHDvm6pSyUg0Luy7jMq9gL37Ar4WR0R6aIBuih4A3tKPmWbKI=; 4:Xha7pYE2cPs8nMhvL4PNffWCgFf91SSMJ34irUsyvOANeSn9MHPDTyOg/DQysQ7zDOScfrxIMvJGWDNxgINHUSY+qTfCpNHRlGA86e3dg4eHzT23DUFPaCbKcvxGisvotea6bF0agvqdlmybFtlU3cLJv3KayRgF7TnT6QbBxeGS0KEJtsnGtvse7+ErOW5Cg4bxAb3G3qh5Q2VsOfmHkbwQQ5JoG2tbCNXhe1sdk7kstyN7GVfptgYUJZN2TBOoE8fd8VGdYcl+xLfNoGfty46OC7kF6mfcYwVu1qyHM0FQKrc5xYOKR60fZTY6FKiLMC7rc7MVma6NLRiS3+f/ksAmuc3QbXdy8bn2suusdwk= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(8121501046)(520078)(520075)(3002001); SRVR:BLUPR0301MB1538; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0301MB1538; X-Forefront-PRVS: 07013D7479 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0301MB1538; 23:UrWlrvfjpWY8/XDJGLQoG81l25umAflmsK4+1GZ?= =?us-ascii?Q?Fo62JSR/qQWRMekfCHZTzonR9AdUl4SQIphRAEPO1hcZzw4AjzuCd1Eimlk5?= =?us-ascii?Q?yX60Er2CeekgvTjy3DMZCGFLzqD2LobDovZ2iuEox35FwQUNcjj90Ic931KU?= =?us-ascii?Q?fZe06b5UoKM1aUxwrkLOFXQ323DHJXGdHjxHHLwOiS7sjX1DOrv0IUXpLQcE?= =?us-ascii?Q?DNZ6q5E2cIs15NYPm5mc2k75Z1mnE6Jie8UFCCzFCUWcT2nxVomJqT7ZBKo6?= =?us-ascii?Q?G0OLPLkeZ6z4y6sokCRkUFWlxcbmniSxxFxn9YTHyPqxy2TXHyRS4CnhzQOa?= =?us-ascii?Q?YN75L02PV5NTKCnqMvqwDwq9He0Np3vWxpm9FAuWBVivNCiqHNUCvhtQMMad?= =?us-ascii?Q?Xi4HbKELuMdtBsuthtoLG9z+gizl4F1ADVwFTGxwyFftmU/zx/mcgcGCom4p?= =?us-ascii?Q?6kzkstBsyYwZ0qlKg1BjfMCQMngCXIQKd9/dIpHhOadAvHV28Fz8YffUJxAH?= =?us-ascii?Q?aaiaIiwJSsG8wbyV8NF9tNKiWLBBTNrXeJEFBT5MblgLkC8NWMILQDDv8CvY?= =?us-ascii?Q?WjPXyahOnfTXYDM8UcvVWwCRbGy4+B1DoSGubzsH0QSaMED26ObTlzZYHw+z?= =?us-ascii?Q?owWR5mf1UOgbaYfz6oDll+j1lwZA9j3j+Gpfk758bjQfFkOoJOq2u2+LU1i0?= =?us-ascii?Q?BFTv70OUS9U9qwG3XfykCImhCWoV/TVofUrKkqucdpB6IPom5pwP3V8b5HSv?= =?us-ascii?Q?h8OwcCv+iGozY4OEus4FpQBWPZjonWagwVXwKHCFLiAyl12JVRbbgeSGKzDM?= =?us-ascii?Q?bJ6TE60Xz6Sq6AIH54hPvfNEelLPo5yh7iBJRT1JaJwODeUvqcQpqDVYDOym?= =?us-ascii?Q?EgnmO07ZlWcS/n31R0fRMWr0OvmhQWTXgCbUlocZ18frOLV/1BDKf4BWUK8a?= =?us-ascii?Q?j0NEmYicCgApljsm3UUlPMIVlgELLGrrMDpoZxZ7Zgl854MtFwv7yUI3294i?= =?us-ascii?Q?NSWG/nbZEWBcoo2fI/A1i5qmyYt4CUmxEDhDdltvnquNPSWUiW02v4soZHAT?= =?us-ascii?Q?tM/5CwIkvicnFFm9nE32EIluKfr21gnVDgtPRv60eGxeCHr+fYLlQLe3EE/c?= =?us-ascii?Q?rZ4dqhwE2vgIkA3umUoqPnL2OG9STGwT8isT1gOvN19zCVOSsJmyS4W+B2JU?= =?us-ascii?Q?WRlloR2Xelnry4cutzxqPWnC/IMzqM/c2MzNO/NzsKbYZPFn2j3/zImglXQl?= =?us-ascii?Q?88U1di752og+SJ9JJaVuZu/3R9BupD17J8Ks2E4e6mNaa4sdWA/Ns4mCchbW?= =?us-ascii?Q?IvA=3D=3D?= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0301MB1538; 5:tHcy9hM1SCHDAnBwDV6OwpQKPYeZXU2lSoYHlRqgRu9tlG2rd/j8WsI6j1ZknPzIjxlkgDtK0Ru2hvRVYdXFBhiX5a8Dd/DDAnlJ9zy6ERuNzaVjqeIT/rJ1AH4ANzYuYv/LzQD5zBYUnXcqgkpEHQ==; 24:xXwqatnL+99eQwGxxKA7UVP5wjf4Mgqydh/x9xYEAmdsSz9iV5sxGtELYLkHH3MegWOYVRRq/uXVQvimkiPD0tYaUlc6bqUuCUGsv02UOTo=; 20:kzPZkqNoL5JTdVLYwbVyUM9nlG0DhuwIhfkJS9OvYo5om7BCOorV1gUGmIHAQkkJZvzOjKrh9ysWuVt9zY/MmA== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2015 08:00:56.3248 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0301MB1538 X-Mailman-Approved-At: Thu, 17 Sep 2015 00:48:29 +0200 Cc: Zhao Qiang , u-boot@lists.denx.de, alison.wang@freescale.com Subject: [U-Boot] [PATCH 1/3] qe: add u-qe support to arm board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Zhao Qiang ls1021 is arm-core and support qe which is u-qe. add u-qe init for arm board. Signed-off-by: Zhao Qiang --- arch/arm/include/asm/arch-ls102xa/config.h | 4 ++++ arch/arm/include/asm/global_data.h | 8 ++++++++ drivers/Makefile | 1 + drivers/qe/Makefile | 3 ++- drivers/qe/fdt.c | 2 ++ drivers/qe/qe.c | 15 +++++++++++++++ drivers/qe/qe.h | 1 + 7 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a500b5b..9c1b520 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -69,6 +69,10 @@ #define DCU_LAYER_MAX_NUM 16 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + #define CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_LS102XA diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index c69d064..438f128 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -17,6 +17,14 @@ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif + +#if defined(CONFIG_U_QE) + u32 qe_clk; + u32 brg_clk; + uint mp_alloc_base; + uint mp_alloc_top; +#endif /* CONFIG_U_QE */ + #ifdef CONFIG_AT91FAMILY /* "static data" needed by at91's clock.c */ unsigned long cpu_clk_rate_hz; diff --git a/drivers/Makefile b/drivers/Makefile index d8361d9..5ff3943 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -16,6 +16,7 @@ obj-y += twserial/ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ +obj-$(CONFIG_U_QE) += qe/ obj-y += memory/ obj-y += pwm/ obj-y += input/ diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile index 7f1bd06..8fa4866 100644 --- a/drivers/qe/Makefile +++ b/drivers/qe/Makefile @@ -4,5 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := qe.o uccf.o uec.o uec_phy.o +obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o +obj-$(CONFIG_U_QE) += qe.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c index d9a7d82..dfae4bf 100644 --- a/drivers/qe/fdt.c +++ b/drivers/qe/fdt.c @@ -12,6 +12,7 @@ #include #include "qe.h" +#ifdef CONFIG_QE DECLARE_GLOBAL_DATA_PTR; /* @@ -72,3 +73,4 @@ void ft_qe_setup(void *blob) "clock-frequency", gd->arch.qe_clk / 2, 1); fdt_fixup_qe_firmware(blob); } +#endif diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 4358a91..b545ec9 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -40,6 +40,7 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) return; } +#ifdef CONFIG_QE uint qe_muram_alloc(uint size, uint align) { uint retloc; @@ -70,6 +71,7 @@ uint qe_muram_alloc(uint size, uint align) return retloc; } +#endif void *qe_muram_addr(uint offset) { @@ -180,6 +182,17 @@ void qe_init(uint qe_base) qe_snums_init(); } +#ifdef CONFIG_U_QE +void u_qe_init(void) +{ + uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */ + qe_immr = (qe_map_t *)qe_base; + + qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); + out_be32(&qe_immr->iram.iready, QE_IRAM_READY); +} +#endif + void qe_reset(void) { qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID, @@ -212,6 +225,7 @@ void qe_assign_page(uint snum, uint para_ram_base) #define BRG_CLK (gd->arch.brg_clk) +#ifdef CONFIG_QE int qe_set_brg(uint brg, uint rate) { volatile uint *bp; @@ -239,6 +253,7 @@ int qe_set_brg(uint brg, uint rate) return 0; } +#endif /* Set ethernet MII clock master */ diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index ebb7c5f..30484b8 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -275,6 +275,7 @@ void *qe_muram_addr(uint offset); int qe_get_snum(void); void qe_put_snum(u8 snum); void qe_init(uint qe_base); +void u_qe_init(void); void qe_reset(void); void qe_assign_page(uint snum, uint para_ram_base); int qe_set_brg(uint brg, uint rate);