From patchwork Thu Sep 3 11:43:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 514001 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 77C2C1401E7 for ; Thu, 3 Sep 2015 21:42:19 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=MooHlSwr; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0859D4B7F3; Thu, 3 Sep 2015 13:42:08 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6dTtxD0vxU5J; Thu, 3 Sep 2015 13:42:07 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 376034B7CC; Thu, 3 Sep 2015 13:41:45 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AA9C74B779 for ; Thu, 3 Sep 2015 13:41:34 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Hv1cyoFhabZa for ; Thu, 3 Sep 2015 13:41:34 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f46.google.com (mail-pa0-f46.google.com [209.85.220.46]) by theia.denx.de (Postfix) with ESMTPS id 20B4A4B768 for ; Thu, 3 Sep 2015 13:41:30 +0200 (CEST) Received: by pacwi10 with SMTP id wi10so44586646pac.3 for ; Thu, 03 Sep 2015 04:41:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=qKlroyykO1SO1rDa/8e4tNJLYtNIUKkzMyd3rhoVQFQ=; b=MooHlSwrE18QWo2RZjzf5emGLzPRE2LSbeZ54WcYJzjKrz+yUGkCrEAhPRNT1nzyXJ RNpdtVvZRLCDuKKfj+zynCmoTI/57z3/YyWHyYC/abSvcPV9M6rbSgDZM+DhnT9j/e18 OPaRL1m1g0whaLMDIGfMUi0r7l7KWViHvtuECB4rObjyQqsMeNhRGVvsKi9/m15SbCLD eb7xjI51cMhnlxelJAKTS9awVXY958bxaL7qbJmYwir2U2+S4pp090iWv7ZmNnaAzI65 iKLmn4ssugUGhgTN0FdUh2L2zxOQ73bQuTX1ZfoJUuAH7Ek8Oj22IoETXQD8vvhjvPBD i/Pg== X-Received: by 10.68.221.198 with SMTP id qg6mr67080481pbc.147.1441280489305; Thu, 03 Sep 2015 04:41:29 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id o3sm24849880pap.37.2015.09.03.04.41.28 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 03 Sep 2015 04:41:28 -0700 (PDT) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Thu, 3 Sep 2015 04:43:40 -0700 Message-Id: <1441280627-29714-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1441280627-29714-1-git-send-email-bmeng.cn@gmail.com> References: <1441280627-29714-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 04/11] x86: Convert to use driver model pci on quark/galileo X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move to driver model pci for Intel quark/galileo. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v3: None Changes in v2: - Remove arch/x86/cpu/quark/pci.c completely arch/x86/cpu/quark/Makefile | 1 - arch/x86/cpu/quark/pci.c | 70 --------------------------------------------- arch/x86/cpu/quark/quark.c | 5 ---- arch/x86/dts/galileo.dts | 8 ++++-- configs/galileo_defconfig | 1 + include/configs/galileo.h | 12 -------- 6 files changed, 7 insertions(+), 90 deletions(-) delete mode 100644 arch/x86/cpu/quark/pci.c diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile index e87b424..8f1d018 100644 --- a/arch/x86/cpu/quark/Makefile +++ b/arch/x86/cpu/quark/Makefile @@ -6,4 +6,3 @@ obj-y += car.o dram.o msg_port.o quark.o obj-y += mrc.o mrc_util.o hte.o smc.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/quark/pci.c b/arch/x86/cpu/quark/pci.c deleted file mode 100644 index 354e15a..0000000 --- a/arch/x86/cpu/quark/pci.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2015, Bin Meng - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void board_pci_setup_hose(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_PREF_BUS, - CONFIG_PCI_PREF_PHYS, - CONFIG_PCI_PREF_SIZE, - PCI_REGION_PREFETCH); - - pci_set_region(hose->regions + 3, - 0, - 0, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; -} - -int board_pci_post_scan(struct pci_controller *hose) -{ - return 0; -} - -int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) -{ - /* - * TODO: - * - * For some unknown reason, the PCI enumeration process hangs - * when it scans to the PCIe root port 0 (D23:F0) & 1 (D23:F1). - * - * For now we just skip these two devices, and this needs to - * be revisited later. - */ - if (dev == QUARK_HOST_BRIDGE || - dev == QUARK_PCIE0 || dev == QUARK_PCIE1) { - return 1; - } - - return 0; -} diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 7c55d9e..dda3c7c 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -136,7 +136,6 @@ static void quark_enable_legacy_seg(void) int arch_cpu_init(void) { - struct pci_controller *hose; int ret; post_code(POST_CPU_INIT); @@ -148,10 +147,6 @@ int arch_cpu_init(void) if (ret) return ret; - ret = pci_early_init_hose(&hose); - if (ret) - return ret; - /* * Quark SoC has some non-standard BARs (excluding PCI standard BARs) * which need be initialized with suggested values diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index d77ff8a..f119bf7 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -54,8 +54,11 @@ pci { #address-cells = <3>; #size-cells = <2>; - compatible = "intel,pci"; - device_type = "pci"; + compatible = "pci-x86"; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000 + 0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; pciuart0: uart@14,5 { compatible = "pci8086,0936.00", @@ -63,6 +66,7 @@ "pciclass,070002", "pciclass,0700", "x86-uart"; + u-boot,dm-pre-reloc; reg = <0x0000a500 0x0 0x0 0x0 0x0 0x0200a510 0x0 0x0 0x0 0x0>; reg-shift = <2>; diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 6ef1090..358e87b 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -11,6 +11,7 @@ CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y +CONFIG_DM_PCI=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 3c3c6e9..b7ec279 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -20,18 +20,6 @@ /* ns16550 UART is memory-mapped in Quark SoC */ #undef CONFIG_SYS_NS16550_PORT_MAPPED -#define CONFIG_PCI_MEM_BUS 0x90000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x20000000 - -#define CONFIG_PCI_PREF_BUS 0xb0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x20000000 - -#define CONFIG_PCI_IO_BUS 0x2000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xe000 - #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP