From patchwork Mon Aug 31 09:52:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 512414 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 988DC1401DA for ; Mon, 31 Aug 2015 19:51:41 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=w4Vcl5mr; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 02E1F4B729; Mon, 31 Aug 2015 11:51:23 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kE6jwHYcu6NJ; Mon, 31 Aug 2015 11:51:22 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D73354B77D; Mon, 31 Aug 2015 11:50:57 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5567C4B729 for ; Mon, 31 Aug 2015 11:50:47 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2GV9QTg0LKnX for ; Mon, 31 Aug 2015 11:50:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f54.google.com (mail-pa0-f54.google.com [209.85.220.54]) by theia.denx.de (Postfix) with ESMTPS id 17EAA4B71C for ; Mon, 31 Aug 2015 11:50:42 +0200 (CEST) Received: by pabzx8 with SMTP id zx8so134410150pab.1 for ; Mon, 31 Aug 2015 02:50:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MDUtK0YDBw0YZZM1auuHXAGcsz0OOv0V+K9GnTujj9s=; b=w4Vcl5mrW2a1Wezd13KddBCUxlmXc2dtWy8SbXLaxjzlUmDoV0lDuHOIRwefleHyGA Nv6q39nc44jFzj+131Q4N+FOFhITJ7jalVFcRpzK7mWBqdgdoiCTvQugxqLRbmAp8GBF fFNh2lGTbqvL7Aoafc4/dGD/oWQDjEo1sGByEcnLKHYxK5IS616S1wc1Z+2DgH76sI66 E+DhVmf0HLFlGVbdwzHHs3G9HSVImsAJEg4So/utb529QWylT7x9XCQVYkUkpgKI+/V/ VwIOiOA0ZdAXtT8pHM8k9qp0uUAnFWWjSEnQtt/khdljiwH4uqiqcMfktrprKI2tFf+b awTQ== X-Received: by 10.68.190.38 with SMTP id gn6mr36264104pbc.125.1441014641562; Mon, 31 Aug 2015 02:50:41 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id dz8sm14003636pab.4.2015.08.31.02.50.40 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 31 Aug 2015 02:50:41 -0700 (PDT) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Mon, 31 Aug 2015 02:52:51 -0700 Message-Id: <1441014773-10902-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1441014773-10902-1-git-send-email-bmeng.cn@gmail.com> References: <1441014773-10902-1-git-send-email-bmeng.cn@gmail.com> Cc: Joe Hershberger Subject: [U-Boot] [PATCH 6/8] net: designware: Add support to PCI designware devices X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Designware ethernet controller is also seen on PCI bus, e.g. on Intel Quark SoC. Add this support in the DM version driver. Signed-off-by: Bin Meng --- drivers/net/designware.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index ae78d21..06d6f6a 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -558,6 +559,20 @@ static int designware_eth_write_hwaddr(struct udevice *dev) return _dw_write_hwaddr(priv, pdata->enetaddr); } +static int designware_eth_bind(struct udevice *dev) +{ + static int num_cards; + char name[20]; + + /* Create a unique device name for PCI type devices */ + if (device_get_uclass_id(dev->parent) == UCLASS_PCI) { + sprintf(name, "eth_designware#%u", num_cards++); + device_set_name(dev, name); + } + + return 0; +} + static int designware_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); @@ -565,6 +580,22 @@ static int designware_eth_probe(struct udevice *dev) u32 iobase = pdata->iobase; int ret; + /* + * If we are on PCI bus, either directly attached to a PCI root port, + * or via a PCI bridge, fill in platdata before we probe the hardware. + */ + if (device_get_uclass_id(dev->parent) == UCLASS_PCI) { + pci_dev_t bdf; + + bdf = pci_get_bdf(dev); + pci_read_config_dword(bdf, PCI_BASE_ADDRESS_0, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase = pci_mem_to_phys(bdf, iobase); + + pdata->iobase = iobase; + pdata->phy_interface = PHY_INTERFACE_MODE_RMII; + } + debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); priv->mac_regs_p = (struct eth_mac_regs *)iobase; priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET); @@ -617,10 +648,18 @@ U_BOOT_DRIVER(eth_designware) = { .id = UCLASS_ETH, .of_match = designware_eth_ids, .ofdata_to_platdata = designware_eth_ofdata_to_platdata, + .bind = designware_eth_bind, .probe = designware_eth_probe, .ops = &designware_eth_ops, .priv_auto_alloc_size = sizeof(struct dw_eth_dev), .platdata_auto_alloc_size = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; + +static struct pci_device_id supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, + { } +}; + +U_BOOT_PCI_DEVICE(eth_designware, supported); #endif