From patchwork Thu Aug 20 09:52:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 508983 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 673AB1401EF for ; Thu, 20 Aug 2015 19:53:54 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=uz+kBYpM; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2DE484B652; Thu, 20 Aug 2015 11:53:53 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id S4fNv61B6oBZ; Thu, 20 Aug 2015 11:53:53 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E6A624B662; Thu, 20 Aug 2015 11:53:47 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DF6464A01C for ; Thu, 20 Aug 2015 11:53:36 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CQVqb8IWGTIk for ; Thu, 20 Aug 2015 11:53:36 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f41.google.com (mail-pa0-f41.google.com [209.85.220.41]) by theia.denx.de (Postfix) with ESMTPS id 0A4E24B61F for ; Thu, 20 Aug 2015 11:53:33 +0200 (CEST) Received: by pacrn3 with SMTP id rn3so3981557pac.1 for ; Thu, 20 Aug 2015 02:53:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=89dvDtOQtJIZbky1JQkcuKgLbx54L+PFXWkOVLf7Iow=; b=uz+kBYpMJ3d+SDLXQx5hPDaYYjkzj/KBgth0fWDoZektBnn0/V8dlIUsVoSs+UOaRR Rw02jdXQfq0wQ+HuWkPPnoWZf5fW+44CEALneMuOJZd9zei2tf8ju8/NacMv215xro3H FCm/4Vc+CMk5AbHnPge0EmmX/MZSsZ8DSY44TIy0SVAPc+fs9OSWGlzxrDsJHfLe4Dy+ omrnma4HMy7YVAZU6n2G+BavVbmdhwXG5mAmAgttcUQ9hln9ThJoSYX68W140k3c3NYI bnv49DT575qrDOH7lmlyCu1rE9HTjZdzEaIBUuXM531ERedT8dJ8wgGFP4xKPULFZRse ndYQ== X-Received: by 10.68.230.33 with SMTP id sv1mr4917513pbc.160.1440064412099; Thu, 20 Aug 2015 02:53:32 -0700 (PDT) Received: from localhost (port-5873.pppoe.wtnet.de. [84.46.23.8]) by smtp.gmail.com with ESMTPSA id pt3sm3717925pbb.38.2015.08.20.02.53.30 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Aug 2015 02:53:31 -0700 (PDT) From: Thierry Reding To: Albert Aribaud Date: Thu, 20 Aug 2015 11:52:15 +0200 Message-Id: <1440064335-25909-3-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1440064335-25909-1-git-send-email-thierry.reding@gmail.com> References: <1440064335-25909-1-git-send-email-thierry.reding@gmail.com> Cc: u-boot@lists.denx.de, Marc Zyngier Subject: [U-Boot] [PATCH 3/3] armv8/gic: Fix GIC v2 initialization X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thierry Reding Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable interrupts to the primary CPU. This fixes issues seen after booting a Linux kernel from U-Boot. Suggested-by: Marc Zyngier Suggested-by: Mark Rutland Cc: Albert Aribaud Cc: Mark Rutland Cc: Marc Zyngier Signed-off-by: Thierry Reding --- arch/arm/lib/gic_64.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index a3e18f7713e5..62d0022408bc 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -46,11 +46,19 @@ ENTRY(gic_init_secure) ldr w9, [x0, GICD_TYPER] and w10, w9, #0x1f /* ITLinesNumber */ cbz w10, 1f /* No SPIs */ - add x11, x0, (GICD_IGROUPRn + 4) + add x11, x0, GICD_IGROUPRn mov w9, #~0 /* Config SPIs as Grp1 */ + str w9, [x11], #0x4 0: str w9, [x11], #0x4 sub w10, w10, #0x1 cbnz w10, 0b + + ldr x1, =GICC_BASE /* GICC_CTLR */ + mov w0, #3 /* EnableGrp0 | EnableGrp1 */ + str w0, [x1] + + mov w0, #1 << 7 /* allow NS access to GICC_PMR */ + str w0, [x1, #4] /* GICC_PMR */ #endif 1: ret