From patchwork Sat Aug 15 07:07:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 507785 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 97F881402B1 for ; Mon, 17 Aug 2015 17:06:01 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Bjq2s1hP; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DB57A4B7C3; Mon, 17 Aug 2015 09:04:49 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ym02NuoYRUDf; Mon, 17 Aug 2015 09:04:49 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 32E2B4B662; Mon, 17 Aug 2015 09:03:45 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1DDA24B635 for ; Sat, 15 Aug 2015 09:05:40 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8Q3hwKXqlq7k for ; Sat, 15 Aug 2015 09:05:40 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f177.google.com (mail-pd0-f177.google.com [209.85.192.177]) by theia.denx.de (Postfix) with ESMTPS id 91C244B62A for ; Sat, 15 Aug 2015 09:05:36 +0200 (CEST) Received: by pdco4 with SMTP id o4so38441666pdc.3 for ; Sat, 15 Aug 2015 00:05:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=STZRyrNOGARPK2EjqPHH/QaBLsHcm1eksi2CEBuJOH4=; b=Bjq2s1hPN3LNsBPeBhQfPkjtw5wPVTLS2v6dO+4+RV1YzVMlmk74OS1rEKcEvhMyZq DvcZezeS8S0WBMDEqFL2LS8SFvhFG2JcXNfmvyrC6x6tZ2brLeGKBFFIfHEG4/3nxj3j bJBHMMBDa8ImW6l3dzUrxj+dAhEuHreAjb4IP8GW8+s8RcfjMNVCFsMNAVUXJ+ZpNDqh Kq+9ncvmabkeskrrqftlRESLr20frXp+Jfy7afYwVdexC/8yLmyaeVPGTAig7e8nZYEM Em5G1/onDhxoeJL1uZd3sk5qUXAznQMpw8ihPrEcOiRf85cRzeZI8lnpk46VPHre+WVJ fL5w== X-Received: by 10.70.3.98 with SMTP id b2mr95377360pdb.107.1439622334946; Sat, 15 Aug 2015 00:05:34 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id nj9sm8015771pdb.77.2015.08.15.00.05.34 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 15 Aug 2015 00:05:34 -0700 (PDT) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Sat, 15 Aug 2015 00:07:47 -0700 Message-Id: <1439622470-10803-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1439622470-10803-1-git-send-email-bmeng.cn@gmail.com> References: <1439622470-10803-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 5/8] drivers: serial: Add ns16550 compatible pci uart driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a new driver to support National Semiconductor 16550 compatible UART device with PCI interface. The initial support only adds device IDs for Intel Topcliff chipset UART devices. Signed-off-by: Bin Meng --- drivers/serial/Kconfig | 9 ++++++ drivers/serial/Makefile | 1 + drivers/serial/serial_pci.c | 75 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 drivers/serial/serial_pci.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index fd126a8..f2eccdd 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -128,3 +128,12 @@ config X86_SERIAL enabled in the device tree with the correct input clock frequency provided (default 1843200). Enable this to obtain serial console output. + +config PCI_SERIAL + bool "Support for 16550 serial port on PCI bus" + depends on DM_PCI + default n + help + This is the UART driver for ns16550 compatible chipset with PCI + interface. This can be enabled in the device tree with the correct + properties provided. If unsure, say N. diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 1d1f036..a7e2cd2 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o obj-$(CONFIG_X86_SERIAL) += serial_x86.o +obj-$(CONFIG_PCI_SERIAL) += serial_pci.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o ifndef CONFIG_SPL_BUILD diff --git a/drivers/serial/serial_pci.c b/drivers/serial/serial_pci.c new file mode 100644 index 0000000..bc87c9a --- /dev/null +++ b/drivers/serial/serial_pci.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * This driver aims to support National Semiconductor 16550 compatible + * UART device with PCI interface. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct pci_device_id supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_UART_0) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_UART_1) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_UART_2) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_UART_3) }, + {} +}; + +static const struct udevice_id pci_serial_ids[] = { + { .compatible = "pci-uart" }, + { } +}; + +static int pci_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + struct fdt_pci_addr pci_addr; + u32 bar; + int ret; + + /* we prefer to use a memory-mapped register */ + ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, + FDT_PCI_SPACE_MEM32, "reg", &pci_addr); + if (ret) { + /* try if there is any i/o-mapped register */ + ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, + FDT_PCI_SPACE_IO, "reg", &pci_addr); + if (ret) + return ret; + } + + ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset, + &pci_addr, &bar); + if (ret) + return ret; + + plat->base = bar; + plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "reg-shift", 1); + plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 1843200); + + return 0; +} + +U_BOOT_DRIVER(serial_pci) = { + .name = "serial_pci", + .id = UCLASS_SERIAL, + .of_match = pci_serial_ids, + .ofdata_to_platdata = pci_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_PCI_DEVICE(serial_pci, supported);