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CY1PR0301MB0682; 5:lA7yWIMvZfrI98zxDNxqsh8SMosUH+gGOmvhfD1M7VD9zSQnLOkQVGDTA8d8bR2W/jLtRXlo+NYC3UzuXgZb06O5YZ/jv6EBmyRfnvxv8yNGmLDfwcap96yc6J17ddqg9KhEpnWArg4M0K5HrqbbZQ==; 24:alcWmm8UwbGRbluM1YC80XzZTo2RnRkN1GtBM/KPlYgqxA7y447OyejaIb4M4BQgM3xpDFQC2gnP2zTh/QkPXCVsd04bXaiiEeAkfolqdBo=; 20:Kt0KrBvmeQIcHcRk14Mlnw7+u+Uiu+Sjnl3tg+Ek6JbCvBp7snQtCwvJzaIry2x6/fseh4yA6EXv686CDkGVgQ== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2015 02:55:55.3181 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB0682 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V2 4/5] imx: mxs: reimplement get_cpu_rev X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Rewrite get_cpu_rev, from "static const char *get_cpu_rev(void)" to "u32 get_cpu_rev(void)". To align with get_cpu_rev of other i.MXes. Also write get_imx_type to replace get_cpu_type, since we have macro named get_cpu_type. Signed-off-by: Peng Fan Cc: Stefano Babic Reviewed-by: Stefano Babic --- Changes v2: none. arch/arm/cpu/arm926ejs/mxs/mxs.c | 52 ++++++++++++++----------------- arch/arm/include/asm/arch-mxs/sys_proto.h | 1 + 2 files changed, 25 insertions(+), 28 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index ef130ae..30dbf5e 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -132,23 +132,7 @@ int arch_cpu_init(void) return 0; } -#if defined(CONFIG_DISPLAY_CPUINFO) -static const char *get_cpu_type(void) -{ - struct mxs_digctl_regs *digctl_regs = - (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; - - switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { - case HW_DIGCTL_CHIPID_MX23: - return "23"; - case HW_DIGCTL_CHIPID_MX28: - return "28"; - default: - return "??"; - } -} - -static const char *get_cpu_rev(void) +u32 get_cpu_rev(void) { struct mxs_digctl_regs *digctl_regs = (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; @@ -158,38 +142,50 @@ static const char *get_cpu_rev(void) case HW_DIGCTL_CHIPID_MX23: switch (rev) { case 0x0: - return "1.0"; case 0x1: - return "1.1"; case 0x2: - return "1.2"; case 0x3: - return "1.3"; case 0x4: - return "1.4"; + return (MXC_CPU_MX23 << 12) | (rev + 0x10); default: - return "??"; + return 0; } case HW_DIGCTL_CHIPID_MX28: switch (rev) { case 0x1: - return "1.2"; + return (MXC_CPU_MX28 << 12) | 0x12; default: - return "??"; + return 0; } default: + return 0; + } +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +const char *get_imx_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_MX23: + return "23"; /* Quad-Plus version of the mx6 */ + case MXC_CPU_MX28: + return "28"; /* Dual-Plus version of the mx6 */ + default: return "??"; } } int print_cpuinfo(void) { + u32 cpurev; struct mxs_spl_data *data = (struct mxs_spl_data *) ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); - printf("CPU: Freescale i.MX%s rev%s at %d MHz\n", - get_cpu_type(), - get_cpu_rev(), + cpurev = get_cpu_rev(); + printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + get_imx_type((cpurev & 0xFF000) >> 12), + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode); return 0; diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 4678723..d6e9fdb 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -11,6 +11,7 @@ #define __SYS_PROTO_H__ #include +#include <../arch-imx/cpu.h> int mxs_reset_block(struct mxs_register_32 *reg); int mxs_wait_mask_set(struct mxs_register_32 *reg,