diff mbox

[U-Boot,V5,2/6] imx: mx6: ccm: Change the clock settings for i.MX6QP

Message ID 1436585927-18677-2-git-send-email-Peng.Fan@freescale.com
State Awaiting Upstream
Headers show

Commit Message

Peng Fan July 11, 2015, 3:38 a.m. UTC 
Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.

In c files, use runtime check and discard #ifdef.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
---

Changes v5:
 Add Stefano's Acked-by

Changes v4:
 Add Fabio's Reviewed-by

Changes v3:
 Move bit definition to crm_regs.h.

Changes v2:
  1. Remove #ifdef, but use runtime check
  2. A few bit definitions are introduced in c files, because to other platforms
     the macro will make compilation fail, also there are no other places refer
     the bit macro definitions.

 arch/arm/cpu/armv7/mx6/clock.c           | 30 +++++++++++++-------
 arch/arm/cpu/armv7/mx6/soc.c             |  5 +++-
 arch/arm/include/asm/arch-mx6/crm_regs.h | 48 +++++++++++++++++---------------
 3 files changed, 49 insertions(+), 34 deletions(-)

Comments

Stefano Babic Aug. 2, 2015, 8:44 a.m. UTC | #1 
On 11/07/2015 05:38, Peng Fan wrote:
> Since i.MX6QP changes some CCM registers, so modify the clocks settings to
> follow the hardware changes.
> 
> In c files, use runtime check and discard #ifdef.
> 
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Signed-off-by: Ye.Li <B37916@freescale.com>
> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
> Acked-by: Stefano Babic <sbabic@denx.de>
> ---
> 
> Changes v5:
>  Add Stefano's Acked-by
> 
> Changes v4:
>  Add Fabio's Reviewed-by
> 
> Changes v3:
>  Move bit definition to crm_regs.h.
> 
> Changes v2:
>   1. Remove #ifdef, but use runtime check
>   2. A few bit definitions are introduced in c files, because to other platforms
>      the macro will make compilation fail, also there are no other places refer
>      the bit macro definitions.
> 
>  arch/arm/cpu/armv7/mx6/clock.c           | 30 +++++++++++++-------
>  arch/arm/cpu/armv7/mx6/soc.c             |  5 +++-
>  arch/arm/include/asm/arch-mx6/crm_regs.h | 48 +++++++++++++++++---------------
>  3 files changed, 49 insertions(+), 34 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> index b461898..cd4bfdd 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -310,10 +310,12 @@ static u32 get_ipg_per_clk(void)
>  	u32 reg, perclk_podf;
>  
>  	reg = __raw_readl(&imx_ccm->cscmr1);
> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> -	if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
> -		return MXC_HCLK; /* OSC 24Mhz */
> -#endif
> +	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
> +	    is_mx6dqp()) {
> +		if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
> +			return MXC_HCLK; /* OSC 24Mhz */
> +	}
> +
>  	perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
>  
>  	return get_ipg_clk() / (perclk_podf + 1);
> @@ -324,10 +326,13 @@ static u32 get_uart_clk(void)
>  	u32 reg, uart_podf;
>  	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
>  	reg = __raw_readl(&imx_ccm->cscdr1);
> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> -	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
> -		freq = MXC_HCLK;
> -#endif
> +
> +	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
> +	    is_mx6dqp()) {
> +		if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
> +			freq = MXC_HCLK;
> +	}
> +
>  	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
>  	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
>  
> @@ -339,8 +344,13 @@ static u32 get_cspi_clk(void)
>  	u32 reg, cspi_podf;
>  
>  	reg = __raw_readl(&imx_ccm->cscdr2);
> -	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
> -	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
> +	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
> +		     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
> +
> +	if (is_mx6dqp()) {
> +		if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
> +			return MXC_HCLK / (cspi_podf + 1);
> +	}
>  
>  	return	decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
>  }
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index d3a3b2e..e80c09c 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -342,9 +342,12 @@ static void set_ahb_rate(u32 val)
>  static void clear_mmdc_ch_mask(void)
>  {
>  	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +	u32 reg;
> +	reg = readl(&mxc_ccm->ccdr);
>  
>  	/* Clear MMDC channel mask */
> -	writel(0, &mxc_ccm->ccdr);
> +	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
> +	writel(reg, &mxc_ccm->ccdr);
>  }
>  
>  static void init_bandgap(void)
> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
> index 98415ac..7d9fe73 100644
> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
> @@ -123,6 +123,8 @@ struct mxc_ccm_reg {
>  /* Define the bits in register CCDR */
>  #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK			(1 << 16)
>  #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK			(1 << 17)
> +/* Exists on i.MX6QP */
> +#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG		(1 << 18)
>  
>  /* Define the bits in register CSR */
>  #define MXC_CCM_CSR_COSC_READY				(1 << 5)
> @@ -195,10 +197,8 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	8
>  #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
>  #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
> -#ifndef CONFIG_MX6SX
> -#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL			(1 << 1)
> -#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL			(1 << 0)
> -#endif
> +/* Exists on i.MX6QP */
> +#define MXC_CCM_CBCMR_PRE_CLK_SEL			(1 << 1)
>  
>  /* Define the bits in register CSCMR1 */
>  #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK		(0x3 << 29)
> @@ -229,10 +229,10 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK		(0x7 << 7)
>  #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET		7
>  #endif
> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> -#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK			(1 << 6)
> +/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
> +#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
>  #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET		6
> -#endif
> +
>  #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK			0x3F
>  
>  /* Define the bits in register CSCMR2 */
> @@ -244,15 +244,12 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		19
>  #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(1 << 11)
>  #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
> -#ifdef CONFIG_MX6SX
> +/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
>  #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3 << 8)
>  #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		8
> +
>  #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK		(0x3F << 2)
>  #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET		2
> -#else
> -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3F << 2)
> -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		2
> -#endif
>  
>  /* Define the bits in register CSCDR1 */
>  #ifndef CONFIG_MX6SX
> @@ -273,16 +270,10 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
>  #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
>  #endif
> -#ifdef CONFIG_MX6SL
> -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x1F
> -#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
> -#else
>  #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
> -#ifdef CONFIG_MX6SX
> -#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
> -#endif
> -#endif
>  #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
> +/* UART_CLK_SEL exists on i.MX6SL/SX/QP */
> +#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
>  
>  /* Define the bits in register CS1CDR */
>  #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK		(0x3F << 25)
> @@ -316,9 +307,14 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
>  #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		18
>  #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)			(((v) & 0x7) << 18)
> -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x3 << 16)
> -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		16
> -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x3) << 16)
> +
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK	\
> +	(is_mx6dqp() ? (0x7 << 15) : (0x3 << 16))
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET	\
> +	(is_mx6dqp() ? 15 : 16)
> +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)		\
> +	(is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16))
> +
>  #endif
>  #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
>  #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		12
> @@ -384,6 +380,9 @@ struct mxc_ccm_reg {
>  /* Define the bits in register CSCDR2 */
>  #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
>  #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
> +/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
> +#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
> +
>  /* All IPU2_DI1 are LCDIF1 on MX6SX */
>  #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
>  #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	15
> @@ -728,6 +727,9 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CCGR5_SAI2_MASK				(3 << MXC_CCM_CCGR5_SAI2_OFFSET)
>  #endif
>  
> +/* PRG_CLK0 exists on i.MX6QP */
> +#define MXC_CCM_CCGR6_PRG_CLK0_MASK		(3 << 24)
> +
>  #define MXC_CCM_CCGR6_USBOH3_OFFSET		0
>  #define MXC_CCM_CCGR6_USBOH3_MASK		(3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
>  #define MXC_CCM_CCGR6_USDHC1_OFFSET		2
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index b461898..cd4bfdd 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -310,10 +310,12 @@  static u32 get_ipg_per_clk(void)
 	u32 reg, perclk_podf;
 
 	reg = __raw_readl(&imx_ccm->cscmr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-	if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
-		return MXC_HCLK; /* OSC 24Mhz */
-#endif
+	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+	    is_mx6dqp()) {
+		if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+			return MXC_HCLK; /* OSC 24Mhz */
+	}
+
 	perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 
 	return get_ipg_clk() / (perclk_podf + 1);
@@ -324,10 +326,13 @@  static u32 get_uart_clk(void)
 	u32 reg, uart_podf;
 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
-		freq = MXC_HCLK;
-#endif
+
+	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+	    is_mx6dqp()) {
+		if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+			freq = MXC_HCLK;
+	}
+
 	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 
@@ -339,8 +344,13 @@  static u32 get_cspi_clk(void)
 	u32 reg, cspi_podf;
 
 	reg = __raw_readl(&imx_ccm->cscdr2);
-	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
-	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
+		     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+	if (is_mx6dqp()) {
+		if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+			return MXC_HCLK / (cspi_podf + 1);
+	}
 
 	return	decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 }
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index d3a3b2e..e80c09c 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -342,9 +342,12 @@  static void set_ahb_rate(u32 val)
 static void clear_mmdc_ch_mask(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg;
+	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	writel(0, &mxc_ccm->ccdr);
+	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
+	writel(reg, &mxc_ccm->ccdr);
 }
 
 static void init_bandgap(void)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 98415ac..7d9fe73 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -123,6 +123,8 @@  struct mxc_ccm_reg {
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK			(1 << 16)
 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK			(1 << 17)
+/* Exists on i.MX6QP */
+#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG		(1 << 18)
 
 /* Define the bits in register CSR */
 #define MXC_CCM_CSR_COSC_READY				(1 << 5)
@@ -195,10 +197,8 @@  struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	8
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
-#ifndef CONFIG_MX6SX
-#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL			(1 << 1)
-#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL			(1 << 0)
-#endif
+/* Exists on i.MX6QP */
+#define MXC_CCM_CBCMR_PRE_CLK_SEL			(1 << 1)
 
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK		(0x3 << 29)
@@ -229,10 +229,10 @@  struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK		(0x7 << 7)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET		7
 #endif
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
-#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK			(1 << 6)
+/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET		6
-#endif
+
 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK			0x3F
 
 /* Define the bits in register CSCMR2 */
@@ -244,15 +244,12 @@  struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		19
 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(1 << 11)
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
-#ifdef CONFIG_MX6SX
+/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3 << 8)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		8
+
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK		(0x3F << 2)
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET		2
-#else
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3F << 2)
-#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		2
-#endif
 
 /* Define the bits in register CSCDR1 */
 #ifndef CONFIG_MX6SX
@@ -273,16 +270,10 @@  struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
 #endif
-#ifdef CONFIG_MX6SL
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x1F
-#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
-#else
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
-#ifdef CONFIG_MX6SX
-#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
-#endif
-#endif
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
+/* UART_CLK_SEL exists on i.MX6SL/SX/QP */
+#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
 
 /* Define the bits in register CS1CDR */
 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK		(0x3F << 25)
@@ -316,9 +307,14 @@  struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		18
 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)			(((v) & 0x7) << 18)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		(0x3 << 16)
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		16
-#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			(((v) & 0x3) << 16)
+
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK	\
+	(is_mx6dqp() ? (0x7 << 15) : (0x3 << 16))
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET	\
+	(is_mx6dqp() ? 15 : 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)		\
+	(is_mx6dqp() ? (((v) & 0x7) << 15) : (((v) & 0x3) << 16))
+
 #endif
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		12
@@ -384,6 +380,9 @@  struct mxc_ccm_reg {
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
+/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
+
 /* All IPU2_DI1 are LCDIF1 on MX6SX */
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	15
@@ -728,6 +727,9 @@  struct mxc_ccm_reg {
 #define MXC_CCM_CCGR5_SAI2_MASK				(3 << MXC_CCM_CCGR5_SAI2_OFFSET)
 #endif
 
+/* PRG_CLK0 exists on i.MX6QP */
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK		(3 << 24)
+
 #define MXC_CCM_CCGR6_USBOH3_OFFSET		0
 #define MXC_CCM_CCGR6_USBOH3_MASK		(3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
 #define MXC_CCM_CCGR6_USDHC1_OFFSET		2