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[U-Boot,2/2] sunxi: Cache line size definition

Message ID 1431798731-28845-2-git-send-email-contact@paulk.fr
State Accepted
Delegated to: Hans de Goede
Headers show

Commit Message

Paul Kocialkowski May 16, 2015, 5:52 p.m. UTC 
Sunxi platforms use ARM Cortex A8, A7 and A15 (unsupported yet) CPU cores,
which all have 64 bytes cache line size.

This is required to e.g. enable USB gadget.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 include/configs/sunxi-common.h | 3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 723067e..3e4e26b 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -66,6 +66,9 @@ 
 # define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
 #endif
 
+/* CPU */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /* DRAM Base */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define CONFIG_SYS_INIT_RAM_ADDR	0x0