From patchwork Wed May 13 13:45:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 471904 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 63A8C140663 for ; Wed, 13 May 2015 23:52:55 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 113D04B7D4; Wed, 13 May 2015 15:52:54 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nmDUkr7-es4Y; Wed, 13 May 2015 15:52:53 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1E8F74B7C6; Wed, 13 May 2015 15:52:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7BE144B7C6 for ; Wed, 13 May 2015 15:52:48 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kNzUZw7iEfT7 for ; Wed, 13 May 2015 15:52:48 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qk0-f202.google.com (mail-qk0-f202.google.com [209.85.220.202]) by theia.denx.de (Postfix) with ESMTPS id 20E944B7B6 for ; Wed, 13 May 2015 15:52:45 +0200 (CEST) Received: by qkbx191 with SMTP id x191so1202060qkb.0 for ; Wed, 13 May 2015 06:52:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/pm4Uqqu2ZfYZcKzEbmMgoxdnFMhAle6URz+F8+ZFJ0=; b=NvBzJBn6BtayAOnaBL3nrZf61gz1ii7Fm9xLudx7RFUyq0EYCINlBK3IL5rGgnL5iJ e7iWU26pj8onTpPxALp02JeOKQ/JGQthDlckOUi8TVz/vTdWo9MVzYAWHkGGxV8M0skt EuZZj/whjfDovcoO4ze1ErrB+2fFNITeVA7wBXUBylWQWh7Cei+Z87YVVdbS3vhfpB9o DoM27g2ll2Btr1a0F3BWvDpvnOpgcgfA0ZlVJ0BIEDxdfwihB7tdcWEW4uM+insQ/IYf LQy7FId1xNDq2zshO/LOiXRmbp/qs4Q8SiB1E5hgsKkDz+RRLDIE68NSK+O4GLlSy/CH xPsA== X-Gm-Message-State: ALoCoQlIJND+/3HguPyG55z5B1t+IfCHdmbBbiipawoOk52mz6xSQKtWYnrfDMZzkWp16At8zEO3 X-Received: by 10.236.104.129 with SMTP id i1mr35295015yhg.51.1431525164469; Wed, 13 May 2015 06:52:44 -0700 (PDT) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id i27si1082429yha.6.2015.05.13.06.52.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 May 2015 06:52:44 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id D4xRiF30.1; Wed, 13 May 2015 06:52:44 -0700 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 8D94B220F15; Wed, 13 May 2015 07:52:43 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Wed, 13 May 2015 07:45:51 -0600 Message-Id: <1431524760-27290-8-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1431524760-27290-1-git-send-email-sjg@chromium.org> References: <1431524760-27290-1-git-send-email-sjg@chromium.org> Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH v2 07/16] tegra: Introduce SRAM repair on tegra124 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is required in order to avoid instability when running from caches after the kernel starts. Signed-off-by: Simon Glass --- Changes in v2: None arch/arm/include/asm/arch-tegra124/flow.h | 12 ++++++++++++ arch/arm/mach-tegra/powergate.c | 20 +++++++++++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h index 0db1881..ab5cd78 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -26,6 +26,12 @@ struct flow_ctlr { u32 cpu_pwr_csr; /* offset 0x38 */ u32 mpid; /* offset 0x3c */ u32 ram_repair; /* offset 0x40 */ + u32 flow_dbg_sel; /* offset 0x44 */ + u32 flow_dbg_cnt0; /* offset 0x48 */ + u32 flow_dbg_cnt1; /* offset 0x4c */ + u32 flow_dbg_qual; /* offset 0x50 */ + u32 flow_ctlr_spare; /* offset 0x54 */ + u32 ram_repair_cluster1;/* offset 0x58 */ }; /* HALT_COP_EVENTS_0, 0x04 */ @@ -37,4 +43,10 @@ struct flow_ctlr { /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ #define ACTIVE_LP (1 << 0) +/* RAM_REPAIR, 0x40, 0x58 */ +enum { + RAM_REPAIR_REQ = 0x1 << 0, + RAM_REPAIR_STS = 0x1 << 1, +}; + #endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 439cff3..7db348e 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -9,7 +9,7 @@ #include #include - +#include #include #include @@ -75,11 +75,29 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id) return 0; } +static void tegra_powergate_ram_repair(void) +{ +#ifdef CONFIG_TEGRA124 + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; + + /* Request RAM repair for cluster 0 and wait until complete */ + setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); + while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS)) + ; + + /* Same for cluster 1 */ + setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); + while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS)) + ; +#endif +} + int tegra_powergate_sequence_power_up(enum tegra_powergate id, enum periph_id periph) { int err; + tegra_powergate_ram_repair(); reset_set_enable(periph, 1); err = tegra_powergate_power_on(id);