From patchwork Tue May 12 20:55:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 471555 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 25F2B14078C for ; Wed, 13 May 2015 06:57:18 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0B28E4B6BA; Tue, 12 May 2015 22:56:55 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5UKenHzZwMpF; Tue, 12 May 2015 22:56:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 84DF24B6DC; Tue, 12 May 2015 22:56:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9F1014B622 for ; Tue, 12 May 2015 22:55:51 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rVkS81tH_0Tq for ; Tue, 12 May 2015 22:55:51 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yh0-f74.google.com (mail-yh0-f74.google.com [209.85.213.74]) by theia.denx.de (Postfix) with ESMTPS id 03A834B64D for ; Tue, 12 May 2015 22:55:47 +0200 (CEST) Received: by yhl29 with SMTP id 29so597284yhl.1 for ; Tue, 12 May 2015 13:55:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0OU2eA8ljmMwCMYDUw+tgYE9bh4bOt42iwc8oxIdGOs=; b=A9Y03tRp3Wu0v8+by2NvkLqt3ZR7qs3+HJiTtYyUk5g1Qzb5+iiFLN4qAxELL5jvf2 QC1Qe/DICaPM9TSMhXkVuj9EmYaNPhpXfsQxViozkjE38Vl6xK9bZXCgIBiK9zzYYN3P zR/4QZuwNw5SVVTH718Eg6uucu0fJDvbFOdOuvhWvMsBVXqPsiuO2wp1YHF4DmdX1SAz ENLfF7APTdYhfL54RAjck9FIBG0Wh2UmATQ5lex7a73BVOakSu8CZSTsRsZ6Tuyxcr/C 6VVoKuYphqnE/54H10RplbIzVIzYLrj5I9AzoAzlMEqLs82VGLmFxyLwO/nVtZ+h0IC/ Ru+Q== X-Gm-Message-State: ALoCoQlSPWcU9pXv5OtRMxUzWXEJqIw/4VCQIuWz0OS9jwxZRmQByxKzEOh1d8t1Z3N/kuieQRjE X-Received: by 10.140.232.88 with SMTP id d85mr28856347qhc.0.1431464146096; Tue, 12 May 2015 13:55:46 -0700 (PDT) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id f100si958038yhp.7.2015.05.12.13.55.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 May 2015 13:55:46 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id zp7cgbTo.2; Tue, 12 May 2015 13:55:46 -0700 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id AC92622086A; Tue, 12 May 2015 14:55:45 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Tue, 12 May 2015 14:55:15 -0600 Message-Id: <1431464119-21574-15-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1431464119-21574-1-git-send-email-sjg@chromium.org> References: <1431464119-21574-1-git-send-email-sjg@chromium.org> Subject: [U-Boot] [PATCH v2 14/18] rockchip: Add base SoC files X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add some basic files required to allow the SoC to start up. This is a minimal set, enough only to display a serial message in SPL and hang. Signed-off-by: Simon Glass --- Changes in v2: - Tidy up license headers arch/arm/Kconfig | 16 +++ arch/arm/Makefile | 1 + arch/arm/include/asm/arch-rockchip/clock.h | 12 ++ arch/arm/include/asm/arch-rockchip/gpio.h | 5 + arch/arm/include/asm/arch-rockchip/grf.h | 181 +++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 23 ++++ arch/arm/mach-rockchip/Makefile | 12 ++ arch/arm/mach-rockchip/board-spl.c | 54 +++++++++ arch/arm/mach-rockchip/board.c | 17 +++ arch/arm/mach-rockchip/common.c | 11 ++ arch/arm/mach-rockchip/rk3288/Kconfig | 6 + 11 files changed, 338 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/clock.h create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf.h create mode 100644 arch/arm/mach-rockchip/Kconfig create mode 100644 arch/arm/mach-rockchip/Makefile create mode 100644 arch/arm/mach-rockchip/board-spl.c create mode 100644 arch/arm/mach-rockchip/board.c create mode 100644 arch/arm/mach-rockchip/common.c create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c85c728..12320c8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -799,6 +799,20 @@ config TARGET_STM32F429_DISCOVERY bool "Support STM32F429 Discovery" select CPU_V7M +config ARCH_ROCKCHIP + bool "Support Rockchip SoCs" + select SUPPORT_SPL + select SPL + select OF_CONTROL + select CPU_V7 + select DM + select SPL_DM + select DM_SERIAL + select DM_SPI + select DM_SPI_FLASH + select DM_I2C + select DM_GPIO + endchoice source "arch/arm/mach-at91/Kconfig" @@ -833,6 +847,8 @@ source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/cpu/armv7/rmobile/Kconfig" +source "arch/arm/mach-rockchip/Kconfig" + source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" source "arch/arm/mach-socfpga/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6f30098..2a91c04 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -54,6 +54,7 @@ machine-$(CONFIG_ARCH_NOMADIK) += nomadik # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x machine-$(CONFIG_ARCH_SOCFPGA) += socfpga +machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSATILE) += versatile diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h new file mode 100644 index 0000000..9314585 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_CLOCK_H +#define _ASM_ARCH_CLOCK_H + +#define OSC_HZ (24 * 1000 * 1000) + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h new file mode 100644 index 0000000..607949c --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/gpio.h @@ -0,0 +1,5 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ diff --git a/arch/arm/include/asm/arch-rockchip/grf.h b/arch/arm/include/asm/arch-rockchip/grf.h new file mode 100644 index 0000000..8722a89 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf.h @@ -0,0 +1,181 @@ +/* + * (C) Copyright 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + * From coreboot file of the same name + */ + +#ifndef _ASM_ARCH_GRF_H +#define _ASM_ARCH_GRF_H + +struct rk3288_grf_gpio_lh { + u32 l; + u32 h; +}; + +struct rk3288_grf_regs { + u32 reserved[3]; + union { + u32 gpio1d_iomux; + u32 iomux_lcdc; + }; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + union { + u32 gpio2c_iomux; + u32 iomux_i2c3; + }; + u32 reserved2; + union { + u32 gpio3a_iomux; + u32 iomux_emmcdata; + }; + union { + u32 gpio3b_iomux; + u32 iomux_emmcpwren; + }; + union { + u32 gpio3c_iomux; + u32 iomux_emmccmd; + }; + u32 gpio3dl_iomux; + u32 gpio3dh_iomux; + u32 gpio4al_iomux; + u32 gpio4ah_iomux; + u32 gpio4bl_iomux; + u32 reserved3; + u32 gpio4c_iomux; + u32 gpio4d_iomux; + u32 reserved4; + union { + u32 gpio5b_iomux; + u32 iomux_spi0; + }; + u32 gpio5c_iomux; + u32 reserved5; + union { + u32 gpio6a_iomux; + u32 iomux_i2s; + }; + union { + u32 gpio6b_iomux; + u32 iomux_i2c2; + u32 iomux_i2sclk; + }; + union { + u32 gpio6c_iomux; + u32 iomux_sdmmc0; + }; + u32 reserved6; + union { + u32 gpio7a_iomux; + u32 iomux_pwm0; + u32 iomux_pwm1; + }; + union { + u32 gpio7b_iomux; + u32 iomux_edp_hotplug; + }; + union { + u32 gpio7cl_iomux; + u32 iomux_i2c5sda; + u32 iomux_i2c4; + }; + union { + u32 gpio7ch_iomux; + u32 iomux_uart2; + u32 iomux_i2c5scl; + }; + u32 reserved7; + union { + u32 gpio8a_iomux; + u32 iomux_spi2csclk; + u32 iomux_i2c1; + }; + union { + u32 gpio8b_iomux; + u32 iomux_spi2txrx; + }; + u32 reserved8[30]; + struct rk3288_grf_gpio_lh gpio_sr[8]; + u32 gpio1_p[8][4]; + u32 gpio1_e[8][4]; + u32 gpio_smt; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_status[22]; + u32 reserved9[2]; + u32 peridmac_con[4]; + u32 ddrc0_con0; + u32 ddrc1_con0; + u32 cpu_con[5]; + u32 reserved10[3]; + u32 cpu_status0; + u32 reserved11; + u32 uoc0_con[5]; + u32 uoc1_con[5]; + u32 uoc2_con[4]; + u32 uoc3_con[2]; + u32 uoc4_con[2]; + u32 pvtm_con[3]; + u32 pvtm_status[3]; + u32 io_vsel; + u32 saradc_testbit; + u32 tsadc_testbit_l; + u32 tsadc_testbit_h; + u32 os_reg[4]; + u32 reserved12; + u32 soc_con15; + u32 soc_con16; +}; + +struct rk3288_sgrf_regs { + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 reserved1[(0x20-0x18)/4]; + u32 busdmac_con[2]; + u32 reserved2[(0x40-0x28)/4]; + u32 cpu_con[3]; + u32 reserved3[(0x50-0x4c)/4]; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 soc_con16; + u32 soc_con17; + u32 soc_con18; + u32 soc_con19; + u32 soc_con20; + u32 soc_con21; + u32 reserved4[(0x100-0x90)/4]; + u32 soc_status[2]; + u32 reserved5[(0x120-0x108)/4]; + u32 fast_boot_addr; +}; + +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig new file mode 100644 index 0000000..2b58161 --- /dev/null +++ b/arch/arm/mach-rockchip/Kconfig @@ -0,0 +1,23 @@ +if ARCH_ROCKCHIP + +config ROCKCHIP_RK3288 + bool "Support Rockchip RK3288" + help + The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 + including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two + video interfaces supporting HDMI and eDP, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs. + +config SYS_MALLOC_F + default y + +config SYS_MALLOC_F_LEN + default 0x800 + +config ROCKCHIP_SERIAL + default y + +source "arch/arm/mach-rockchip/rk3288/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile new file mode 100644 index 0000000..0cef0a2 --- /dev/null +++ b/arch/arm/mach-rockchip/Makefile @@ -0,0 +1,12 @@ +# +# Copyright (c) 2014 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += board-spl.o +else +obj-y += board.o +endif +obj-y += common.o diff --git a/arch/arm/mach-rockchip/board-spl.c b/arch/arm/mach-rockchip/board-spl.c new file mode 100644 index 0000000..a6e0ec9 --- /dev/null +++ b/arch/arm/mach-rockchip/board-spl.c @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set) +#define IOMUX_UART2 RK_CLRSETBITS(7 << 12 | 3 << 8, 1 << 12 | 1 << 8) +#define GRF_BASE 0xFF770000 + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_SPI; +} + +void spl_board_load_image(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct rk3288_grf_regs * const rk3288_grf = (void *)GRF_BASE; + + writel(IOMUX_UART2, &rk3288_grf->iomux_uart2); + + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} + +void spl_board_init(void) +{ + preloader_console_init(); +} diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c new file mode 100644 index 0000000..38d2b40 --- /dev/null +++ b/arch/arm/mach-rockchip/board.c @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + return 0; +} diff --git a/arch/arm/mach-rockchip/common.c b/arch/arm/mach-rockchip/common.c new file mode 100644 index 0000000..51ea34d --- /dev/null +++ b/arch/arm/mach-rockchip/common.c @@ -0,0 +1,11 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +void reset_cpu(ulong addr) +{ +} diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig new file mode 100644 index 0000000..26d5951 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -0,0 +1,6 @@ +if ROCKCHIP_RK3288 + +config SYS_SOC + default "rockchip" + +endif