@@ -16,15 +16,18 @@ obj-y += pinmux.o
obj-y += usbc.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I_A23) += prcm.o
+obj-$(CONFIG_MACH_SUN8I_A33) += prcm.o
obj-$(CONFIG_MACH_SUN9I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
obj-$(CONFIG_MACH_SUN8I_A23) += rsb.o
+obj-$(CONFIG_MACH_SUN8I_A33) += rsb.o
obj-$(CONFIG_MACH_SUN9I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN8I_A23) += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN8I_A33) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
ifndef CONFIG_SPL_BUILD
@@ -39,5 +42,6 @@ obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
+obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
obj-y += fel_utils.o
endif
@@ -46,7 +46,7 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
-#if defined(CONFIG_MACH_SUN8I_A23)
+#if defined(CONFIG_MACH_SUN8I_A23) || defined(CONFIG_MACH_SUN8I_A33)
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
#else
@@ -70,7 +70,8 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I_A23)
+#elif CONFIG_CONS_INDEX == 5 && \
+ (defined(CONFIG_MACH_SUN8I_A23) || defined(CONFIG_MACH_SUN8I_A33))
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
@@ -96,7 +97,8 @@ void s_init(void)
#endif
#if defined CONFIG_MACH_SUN6I || \
defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN8I_A23
+ defined CONFIG_MACH_SUN8I_A23 || \
+ defined CONFIG_MACH_SUN8I_A33
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
@@ -66,6 +66,8 @@ int print_cpuinfo(void)
puts("CPU: Allwinner A20 (SUN7I)\n");
#elif defined CONFIG_MACH_SUN8I_A23
puts("CPU: Allwinner A23 (SUN8I)\n");
+#elif defined CONFIG_MACH_SUN8I_A33
+ puts("CPU: Allwinner A33 (SUN8I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
@@ -20,7 +20,7 @@ static int rsb_set_device_mode(void);
static void rsb_cfg_io(void)
{
-#if defined CONFIG_MACH_SUN8I_A23
+#if defined CONFIG_MACH_SUN8I_A23 || defined CONFIG_MACH_SUN8I_A33
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
@@ -28,7 +28,11 @@
#endif
#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
+#ifdef CONFIG_MACH_SUN8I_A33
+#define SUNXI_USB_CSR 0x410
+#else
#define SUNXI_USB_CSR 0x404
+#endif
#define SUNXI_USB_PASSBY_EN 1
#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
@@ -103,6 +107,11 @@ static void usb_phy_write(struct sunxi_usbc_hcd *sunxi_usbc, int addr,
int j = 0, usbc_bit = 0;
void *dest = sunxi_usbc_get_io_base(0) + SUNXI_USB_CSR;
+#ifdef CONFIG_MACH_SUN8I_A33
+ /* CSR needs to be explicitly initialized to 0 on A33 */
+ writel(0, dest);
+#endif
+
usbc_bit = 1 << (sunxi_usbc->id * 2);
for (j = 0; j < len; j++) {
/* set the bit address to be written */
@@ -52,11 +52,17 @@ config MACH_SUN8I_A23
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+config MACH_SUN8I_A33
+ bool "sun8i (Allwinner A33)"
+ select CPU_V7
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
endchoice
config DRAM_CLK
int "sunxi dram clock speed"
- default 312 if MACH_SUN6I || MACH_SUN8I_A23
+ default 312 if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
---help---
Set the dram clock speed, valid range 240 - 480, must be a multiple
@@ -73,7 +79,8 @@ endif
config DRAM_ZQ
int "sunxi dram zq value"
- default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I_A23
+ default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I
+ default 123 if MACH_SUN8I_A23 || MACH_SUN8I_A33
default 127 if MACH_SUN7I
---help---
Set the dram zq value.
@@ -156,7 +163,7 @@ endif
config SYS_CLK_FREQ
default 912000000 if MACH_SUN7I
default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I
- default 1008000000 if MACH_SUN8I_A23
+ default 1008000000 if MACH_SUN8I_A23 || MACH_SUN8I_A33
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
@@ -164,6 +171,7 @@ config SYS_CONFIG_NAME
default "sun6i" if MACH_SUN6I
default "sun7i" if MACH_SUN7I
default "sun8i" if MACH_SUN8I_A23
+ default "sun8i" if MACH_SUN8I_A33
config SYS_BOARD
default "sunxi"
@@ -339,7 +347,7 @@ config VIDEO
config VIDEO_HDMI
boolean "HDMI output support"
- depends on VIDEO && !MACH_SUN8I_A23
+ depends on VIDEO && !MACH_SUN8I_A23 && !MACH_SUN8I_A33
default y
---help---
Say Y here to add support for outputting video over HDMI.
@@ -353,7 +361,8 @@ config VIDEO_VGA
config VIDEO_VGA_VIA_LCD
boolean "VGA via LCD controller support"
- depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I_A23)
+ depends on VIDEO
+ depends on MACH_SUN5I || MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
default n
---help---
Say Y here to add support for external DACs connected to the parallel
@@ -116,7 +116,7 @@ static void mmc_pinmux_setup(int sdc)
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
-#elif defined(CONFIG_MACH_SUN8I_A23)
+#elif defined(CONFIG_MACH_SUN8I_A23) || defined(CONFIG_MACH_SUN8I_A33)
if (pins == SUNXI_GPIO_D) {
/* SDC1: PD2-PD7 */
for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
@@ -181,7 +181,7 @@ static void mmc_pinmux_setup(int sdc)
sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
}
-#elif defined(CONFIG_MACH_SUN8I_A23)
+#elif defined(CONFIG_MACH_SUN8I_A23) || defined(CONFIG_MACH_SUN8I_A33)
/* SDC2: PC5-PC6, PC8-PC16 */
for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
@@ -1,6 +1,6 @@
config AXP221_POWER
boolean "axp221 / axp223 pmic support"
- depends on MACH_SUN6I || MACH_SUN8I_A23
+ depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
default y
---help---
Say y here to enable support for the axp221 / axp223 pmic found on most
@@ -47,7 +47,7 @@ config AXP221_ALDO2_VOLT
int "axp221 aldo2 voltage"
depends on AXP221_POWER
default 0 if MACH_SUN6I
- default 2500 if MACH_SUN8I_A23
+ default 2500 if MACH_SUN8I_A23 || MACH_SUN8I_A33
---help---
Set the voltage (mV) to program the axp221 aldo2 at, set to 0 to
disable aldo2. On sun6i (A31) boards this is typically unused and
@@ -458,8 +458,13 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
static inline u8 musb_read_configdata(void __iomem *mbase)
{
+#ifdef CONFIG_MACH_SUN8I_A33
+ /* <Sigh> allwinner saves a reg, and we need to hardcode this */
+ return 0xde;
+#else
musb_writeb(mbase, MUSB_INDEX, 0);
return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
+#endif
}
static inline u16 musb_read_hwvers(void __iomem *mbase)
@@ -947,6 +947,9 @@ static void sunxi_drc_init(void)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* On sun6i the drc must be clocked even when in pass-through mode */
+#ifdef CONFIG_MACH_SUN8I_A33
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
+#endif
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
#endif
@@ -241,7 +241,8 @@ extern int soft_i2c_gpio_scl;
#endif
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"
-#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I_A23)
+#elif CONFIG_CONS_INDEX == 5 && \
+ (defined(CONFIG_MACH_SUN8I_A23) || defined(CONFIG_MACH_SUN8I_A33))
#define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200"
#else
#error Unsupported console port nr. Please fix stdout-path in sunxi-common.h.