From patchwork Sat Apr 25 20:17:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel Huau X-Patchwork-Id: 464600 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EFFF614007D for ; Sun, 26 Apr 2015 06:18:05 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 946744BFA8; Sat, 25 Apr 2015 22:18:04 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0sjbaLILhvHE; Sat, 25 Apr 2015 22:18:04 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1EB044BF8E; Sat, 25 Apr 2015 22:18:04 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CE9C74BF8E for ; Sat, 25 Apr 2015 22:17:59 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AhN0MSwQz5p7 for ; Sat, 25 Apr 2015 22:17:59 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtpout2.mel.teaser.net (smtpout2.mel.teaser.net [213.162.54.61]) by theia.denx.de (Postfix) with ESMTP id 850C04BF8B for ; Sat, 25 Apr 2015 22:17:54 +0200 (CEST) Received: from localhost.localdomain (c-24-18-130-6.hsd1.wa.comcast.net [24.18.130.6]) by smtpout2.mel.teaser.net (Postfix) with ESMTPA id 29B6738C4A; Sat, 25 Apr 2015 22:17:52 +0200 (CEST) From: Gabriel Huau To: u-boot@lists.denx.de, Simon Glass , Graeme Russ Date: Sat, 25 Apr 2015 13:17:41 -0700 Message-Id: <1429993061-10513-1-git-send-email-contact@huau-gabriel.fr> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1429805775-1809-4-git-send-email-contact@huau-gabriel.fr> References: <1429805775-1809-4-git-send-email-contact@huau-gabriel.fr> Cc: Gabriel Huau Subject: [U-Boot] [PATCH 3/4 v2] x86: gpio: add pinctrl support from the device tree X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Signed-off-by: Gabriel Huau --- Changes for v2: - Clean commit message - Rename compatible string 'ich6' to 'x86' - Fix coding style - Create a dt-bindinds documentation - Move x86-gpio defines to a specific header - Reorder the functions to avoid the need for forward declarations - Rename double underscore functions to only one - Create a specific function to configure one pin - Use a define to prevent build/support issues with other x86 CPU that doesn't have a IOBASE. arch/x86/dts/minnowmax.dts | 21 ++ arch/x86/include/asm/arch-baytrail/gpio.h | 1 + arch/x86/include/asm/gpio.h | 1 + .../gpio/intel,x86-pinctrl.txt | 31 +++ drivers/gpio/intel_ich6_gpio.c | 234 ++++++++++++++++++--- include/dt-bindings/gpio/x86-gpio.h | 36 ++++ 6 files changed, 295 insertions(+), 29 deletions(-) create mode 100644 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt create mode 100644 include/dt-bindings/gpio/x86-gpio.h diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index c73e421..ea10963 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include + /include/ "skeleton.dtsi" /include/ "serial.dtsi" @@ -21,6 +23,25 @@ silent_console = <0>; }; + pch_pinctrl { + compatible = "intel,x86-pinctrl"; + pin_usb_host_en0@0 { + gpio-offset = <0x80 8>; + pad-offset = <0x260>; + mode-gpio; + output-value = <1>; + direction = ; + }; + + pin_usb_host_en1@0 { + gpio-offset = <0x80 9>; + pad-offset = <0x258>; + mode-gpio; + output-value = <1>; + direction = ; + }; + }; + gpioa { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index 4e8987c..85a65a8 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -9,5 +9,6 @@ /* Where in config space is the register that points to the GPIO registers? */ #define PCI_CFG_GPIOBASE 0x48 +#define PCI_CFG_IOBASE 0x4c #endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index 1099427..ed85b08 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -147,6 +147,7 @@ struct pch_gpio_map { } set3; }; +int gpio_ich6_pinctrl_init(void); void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio); void ich_gpio_set_gpio_map(const struct pch_gpio_map *map); diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt new file mode 100644 index 0000000..45ab1af --- /dev/null +++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt @@ -0,0 +1,31 @@ +Intel x86 PINCTRL/GPIO controller + +Pin-muxing on x86 can be described with a node for the PINCTRL master +node and a set of child nodes for each pin on the SoC. + +The PINCTRL master node requires the following properties: +- compatible : "intel,x86-pinctrl" + +Pin nodes must be children of the pinctrl master node and can +contain the following properties: +- pad-offset - (required) offset in the IOBASE for the pin to configured. +- gpio-offset - (required) offset in the GPIOBASE for the pin to configured and + also the bit shift in this register. +- mode-gpio - (optional) standalone property to force the pin into GPIO mode. +- mode-func - (optional) function number to assign to the pin. if 'mode-gpio' + is set, this property will be ignored. +in case of 'mode-gpio' property set: +- output-value - (optional) this set the default output value of the GPIO. +- direction - (optional) this set the direction of the gpio. +- pull-str - (optional) this set the pull strength of the pin. +- pull-assign - (optional) this set the pull assignement (up/down) of the pin. + +Example: + +pin_usb_host_en0@0 { + gpio-offset = <0x80 8>; + pad-offset = <0x260>; + mode-gpio; + output-value = <1>; + direction = ; +}; diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 7e679a0..c18c60f 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -44,21 +44,28 @@ struct ich6_bank_priv { uint16_t lvl; }; +#define GPIO_USESEL_OFFSET(x) (x) +#define GPIO_IOSEL_OFFSET(x) (x + 4) +#define GPIO_LVL_OFFSET(x) (x + 8) + +#define IOPAD_MODE_MASK 0x7 +#define IOPAD_PULL_ASSIGN_SHIFT 7 +#define IOPAD_PULL_ASSIGN_MASK (0x3 << IOPAD_PULL_ASSIGN_SHIFT) +#define IOPAD_PULL_STRENGTH_SHIFT 9 +#define IOPAD_PULL_STRENGTH_MASK (0x3 << IOPAD_PULL_STRENGTH_SHIFT) + /* TODO: Move this to device tree, or platform data */ void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) { gd->arch.gpio_map = map; } -static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) +static int gpio_ich6_get_base(unsigned long base) { - struct ich6_bank_platdata *plat = dev_get_platdata(dev); pci_dev_t pci_dev; /* handle for 0:1f:0 */ u8 tmpbyte; u16 tmpword; u32 tmplong; - u16 gpiobase; - int offset; /* Where should it be? */ pci_dev = PCI_BDF(0, 0x1f, 0); @@ -123,9 +130,9 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) * while on the Ivybridge the bit0 is used to indicate it is an * I/O space. */ - tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE); + tmplong = x86_pci_read_config32(pci_dev, base); if (tmplong == 0x00000000 || tmplong == 0xffffffff) { - debug("%s: unexpected GPIOBASE value\n", __func__); + debug("%s: unexpected BASE value\n", __func__); return -ENODEV; } @@ -135,7 +142,195 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ - gpiobase = tmplong & 0xfffe; + return tmplong & 0xfffc; +} + +static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value) +{ + u32 tmplong; + tmplong = inl(base); + if (value) + tmplong |= (1UL << offset); + else + tmplong &= ~(1UL << offset); + outl(tmplong, base); + + return 0; +} + +static int _ich6_gpio_set_function(uint16_t base, unsigned offset, int func) +{ + u32 tmplong; + + if (func) { + tmplong = inl(base); + tmplong |= (1UL << offset); + outl(tmplong, base); + } else { + tmplong = inl(base); + tmplong &= ~(1UL << offset); + outl(tmplong, base); + } + + return 0; +} + +static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir) +{ + u32 tmplong; + + if (!dir) { + tmplong = inl(base); + tmplong |= (1UL << offset); + outl(tmplong, base); + } else { + tmplong = inl(base); + tmplong &= ~(1UL << offset); + outl(tmplong, base); + } + + return 0; +} + +static int _gpio_ich6_pinctrl_cfg_pin(u32 gpiobase, u32 iobase, int pin_node) +{ + u32 gpio_offset[2] = { -1, -1 }; + u32 pad_offset; + int tmplong; + const void *tmpnode; + + /* + * GPIO node is not mandatory, so we only do the + * pinmuxing if the node exist. + */ + fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset", + gpio_offset, 2); + if (gpio_offset[0] != -1) { + /* Do we want to force the GPIO mode? */ + tmpnode = fdt_getprop(gd->fdt_blob, pin_node, "mode-gpio", + NULL); + if (tmpnode) + _ich6_gpio_set_function(GPIO_USESEL_OFFSET + (gpiobase) + + gpio_offset[0], + gpio_offset[1], 1); + + tmplong = + fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1); + if (tmplong != -1) + _ich6_gpio_set_direction(GPIO_IOSEL_OFFSET + (gpiobase) + + gpio_offset[0], + gpio_offset[1], tmplong); + + tmplong = + fdtdec_get_int(gd->fdt_blob, pin_node, "output-value", -1); + if (tmplong != -1) + _ich6_gpio_set_value(GPIO_LVL_OFFSET(gpiobase) + + gpio_offset[0], + gpio_offset[1], tmplong); + } +#ifdef PCI_CFG_IOBASE + /* + * The offset for the same pin for the IOBASE and GPIOBASE are + * different, so instead of maintaining a lookup table, + * the device tree should provide directly the correct + * value for both mapping. + */ + pad_offset = fdtdec_get_int(gd->fdt_blob, pin_node, "pad-offset", -1); + if (pad_offset == -1) { + debug("%s: Invalid register io offset %d\n", + __func__, pad_offset); + return -EINVAL; + } + + /* + * Do we need to set a specific function mode? + * If someone put also 'mode-gpio', this option will + * be just ignored by the controller + */ + tmplong = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1); + if (tmplong != -1) + clrsetbits_le32(iobase + pad_offset, IOPAD_MODE_MASK, tmplong); + + /* Configure the pull-up/down if needed */ + tmplong = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1); + if (tmplong != -1) + clrsetbits_le32(iobase + pad_offset, + IOPAD_PULL_ASSIGN_MASK, + tmplong << IOPAD_PULL_ASSIGN_SHIFT); + + tmplong = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength", -1); + if (tmplong != -1) + clrsetbits_le32(iobase + pad_offset, + IOPAD_PULL_STRENGTH_MASK, + tmplong << IOPAD_PULL_STRENGTH_SHIFT); + + debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset, + readl(iobase + pad_offset)); +#endif + + return 0; +} + +int gpio_ich6_pinctrl_init(void) +{ + int pin_node; + int node; + int ret; + u32 gpiobase; + u32 iobase; + +#ifdef PCI_CFG_IOBASE + /* + * Get the memory/io base address to configure every pins. + * IOBASE is used to configure the mode/pads + * GPIOBASE is used to configure the direction and default value + */ + iobase = gpio_ich6_get_base(PCI_CFG_IOBASE); + if (iobase < 0) { + debug("%s: invalid IOBASE address (%08x)\n", __func__, iobase); + return -EINVAL; + } +#endif + + gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE); + if (gpiobase < 0) { + debug("%s: invalid GPIOBASE address (%08x)\n", __func__, + gpiobase); + return -EINVAL; + } + + /* This is not an error to not have a pinctrl node */ + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, + "intel,x86-pinctrl"); + if (node < 0) { + debug("%s: no pinctrl node\n", __func__); + return 0; + } + + for (pin_node = fdt_first_subnode(gd->fdt_blob, node); + pin_node > 0; + pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) { + /* Configure the pin */ + ret = _gpio_ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node); + if (ret != 0) { + debug("%s: invalid configuration for the pin %d\n", + __func__, pin_node); + return ret; + } + } + + return 0; +} + +static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) +{ + struct ich6_bank_platdata *plat = dev_get_platdata(dev); + u16 gpiobase; + int offset; + + gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE); offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); if (offset == -1) { debug("%s: Invalid register offset %d\n", __func__, offset); @@ -192,30 +387,19 @@ static int ich6_gpio_request(struct udevice *dev, unsigned offset, static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset) { struct ich6_bank_priv *bank = dev_get_priv(dev); - u32 tmplong; - tmplong = inl(bank->io_sel); - tmplong |= (1UL << offset); - outl(bank->io_sel, tmplong); - return 0; + return _ich6_gpio_set_direction(inl(bank->io_sel), offset, 0); } static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset, int value) { struct ich6_bank_priv *bank = dev_get_priv(dev); - u32 tmplong; - gpio_set_value(offset, value); - - tmplong = inl(bank->io_sel); - tmplong &= ~(1UL << offset); - outl(bank->io_sel, tmplong); - return 0; + return _ich6_gpio_set_direction(inl(bank->io_sel), offset, 1); } static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) - { struct ich6_bank_priv *bank = dev_get_priv(dev); u32 tmplong; @@ -230,15 +414,7 @@ static int ich6_gpio_set_value(struct udevice *dev, unsigned offset, int value) { struct ich6_bank_priv *bank = dev_get_priv(dev); - u32 tmplong; - - tmplong = inl(bank->lvl); - if (value) - tmplong |= (1UL << offset); - else - tmplong &= ~(1UL << offset); - outl(bank->lvl, tmplong); - return 0; + return _ich6_gpio_set_value(bank->lvl, offset, value); } static int ich6_gpio_get_function(struct udevice *dev, unsigned offset) diff --git a/include/dt-bindings/gpio/x86-gpio.h b/include/dt-bindings/gpio/x86-gpio.h new file mode 100644 index 0000000..103bd04 --- /dev/null +++ b/include/dt-bindings/gpio/x86-gpio.h @@ -0,0 +1,36 @@ +/* + * This header provides constants for binding nvidia,tegra*-gpio. + * + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below + * provide names for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_X86_GPIO_H +#define _DT_BINDINGS_GPIO_X86_GPIO_H + +#include + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 + +#define GPIO_MODE_FUNC0 0 +#define GPIO_MODE_FUNC1 1 +#define GPIO_MODE_FUNC2 2 +#define GPIO_MODE_FUNC3 3 +#define GPIO_MODE_FUNC4 4 +#define GPIO_MODE_FUNC5 5 +#define GPIO_MODE_FUNC6 6 + +#define PIN_INPUT 0 +#define PIN_OUTPUT 1 + +#define PIN_INPUT_NOPULL 0 +#define PIN_INPUT_PULLUP 1 +#define PIN_INPUT_PULLDOWN 2 + +#define PULL_STR_2K 0 +#define PULL_STR_20K 2 + +#endif