From patchwork Sat Apr 25 15:04:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 464570 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 49FEA1400B7 for ; Sun, 26 Apr 2015 01:04:56 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 86F114BE7C; Sat, 25 Apr 2015 17:04:53 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Lo698sCJumxZ; Sat, 25 Apr 2015 17:04:53 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E147A4BE0E; Sat, 25 Apr 2015 17:04:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 046B24BE0E for ; Sat, 25 Apr 2015 17:04:50 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nJ3CpmuFuk1I for ; Sat, 25 Apr 2015 17:04:49 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f201.google.com (mail-ob0-f201.google.com [209.85.214.201]) by theia.denx.de (Postfix) with ESMTPS id 7F11D4BE0B for ; Sat, 25 Apr 2015 17:04:46 +0200 (CEST) Received: by obbgq1 with SMTP id gq1so4579065obb.1 for ; Sat, 25 Apr 2015 08:04:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=CFumruIthO9FzllXBm97rDzGe62RUkpvCNOM85B3Sq0=; b=Xy0Wk/dwfCE0cCMxXs1EbaoZfOUhyk6R5IKWU8gGZ7haupFdQO/BKygcFxr4IOtWCW o2NvznHRHxgrZyWt/3QB3cQA84lQC/b7FtXs1elj8x8bDIQSmsEBxVhb/VwC6Mymdc25 hSIWaPKwcma+bN8NggWy6AUkm8DAvNcnBBIjub+eQt9i+b7m8OYh/vNVWBX4C5SFZtiQ LmII5rUD7qwYm22zSHt9TeTpgb0dTFWVaS6vmN9qlKbV5Zz9SKG8mSe6cTsFRxWnPhTU jtOJh7I7Ig6S/12XVislzQW/0shzwZ1T3/s3WtcT6sauwV5+3sqeX3lKIT82AYjKPWZH 72/Q== X-Gm-Message-State: ALoCoQn56VQ6izZgyGupVS9S8UUThml4Mmvwomby5x4AE7G2Du7UgaH6IWPdFKMruT5bsE6elG9o X-Received: by 10.182.96.100 with SMTP id dr4mr5619964obb.31.1429974284653; Sat, 25 Apr 2015 08:04:44 -0700 (PDT) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id r25si828897yho.3.2015.04.25.08.04.44 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 25 Apr 2015 08:04:44 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id wkTPgku6.1; Sat, 25 Apr 2015 08:04:44 -0700 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 7DD6B220851; Sat, 25 Apr 2015 09:04:43 -0600 (MDT) From: Simon Glass To: u-boot@lists.denx.de, Simon Glass , Graeme Russ Date: Sat, 25 Apr 2015 09:04:32 -0600 Message-Id: <1429974275-13743-1-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c Cc: Tom Rini Subject: [U-Boot] [PATCH 1/4] x86: Implement reset_cpu() correctly for modern CPUs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The existing code is pretty ancient and is unreliable on modern hardware. Generally it will hang. We can use port 0xcf9 to initiate reset on more modern hardware (say in the last 10 years). Update the reset_cpu() function to do this, and add a new 'full reset' function to perform a full power cycle. Signed-off-by: Simon Glass --- arch/x86/cpu/cpu.c | 22 +++++++++------------- arch/x86/include/asm/processor.h | 11 +++++++++++ 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index c9614f1..13b3baa 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -380,21 +380,17 @@ void flush_cache(unsigned long dummy1, unsigned long dummy2) asm("wbinvd\n"); } -void __attribute__ ((regparm(0))) generate_gpf(void); - -/* segment 0x70 is an arbitrary segment which does not exist */ -asm(".globl generate_gpf\n" - ".hidden generate_gpf\n" - ".type generate_gpf, @function\n" - "generate_gpf:\n" - "ljmp $0x70, $0x47114711\n"); - __weak void reset_cpu(ulong addr) { - printf("Resetting using x86 Triple Fault\n"); - set_vector(13, generate_gpf); /* general protection fault handler */ - set_vector(8, generate_gpf); /* double fault handler */ - generate_gpf(); /* start the show */ + /* Do a hard reset through the chipset's reset control register */ + outb(SYS_RST | RST_CPU, PORT_RESET); + for (;;) + cpu_hlt(); +} + +void x86_full_reset(void) +{ + outb(FULL_RST, PORT_RESET); } int dcache_status(void) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 3e26202..a24028d 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -27,6 +27,17 @@ #define PORT_RESET 0xcf9 +enum { + SYS_RST = 1 << 1, /* clear for soft reset, set for hard */ + RST_CPU = 1 << 2, /* initiate reset */ + FULL_RST = 1 << 3, /* full power cycle */ +}; + +/** + * x86_full_reset() - reset everything: perform a full power cycle + */ +void x86_full_reset(void); + static inline __attribute__((always_inline)) void cpu_hlt(void) { asm("hlt");