From patchwork Tue Apr 21 13:10:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 463123 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D8EC414012C for ; Tue, 21 Apr 2015 23:10:22 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 496293938; Tue, 21 Apr 2015 15:10:20 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id L_3XYz35BJlF; Tue, 21 Apr 2015 15:10:20 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 91BFC392D; Tue, 21 Apr 2015 15:10:19 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0555F392D for ; Tue, 21 Apr 2015 15:10:17 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UNYzDQP2yZ4l for ; Tue, 21 Apr 2015 15:10:16 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-lb0-f173.google.com (mail-lb0-f173.google.com [209.85.217.173]) by theia.denx.de (Postfix) with ESMTPS id B9BDC3925 for ; Tue, 21 Apr 2015 15:10:13 +0200 (CEST) Received: by lbbzk7 with SMTP id zk7so155244906lbb.0 for ; Tue, 21 Apr 2015 06:10:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=yLU9q4TcHoIzRoqUiUZRkmFg361pmOV6/EefwebRLkw=; b=B3CRuYJVlOEmyvTW3I/8z4Su30mNDCN/ZA3IBJAMwE5+FtouV1o78hKJwt/yXMYgpj HA2CQq0pBnm0JodSCwZjiOEo4nxW1AMMv4w3iXhgBYYeYISd8i9/VD8HzakfHkYaTWEC 75Y5EO9nq4yLnpkd73NuRIjNcQrJBaXoc6DNClBdTnJ8PyF3ErhtQFRPsV4q6p+xahBi nXdwzoqoi1d2yemkKSHg6ftNv9Y4EbSx0IwZmKetjzn0iSUH+VlxNvJF8flroL6oq6mw 4fmqWkT8W5P5tjHEgGM0roFkVlxV7xx5VuQj5F1o/tLtX+rTCT++329g8suXrM67aJ8H mGkg== X-Gm-Message-State: ALoCoQmotEhWy8r2uu0dkGEz/VP7QRHVB6SzoVyHMaypc2Gv1SNfCYRFOY32p0fkhj5f+lhK3Lxh X-Received: by 10.152.115.173 with SMTP id jp13mr19763052lab.119.1429621812847; Tue, 21 Apr 2015 06:10:12 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id o7sm386624lbp.37.2015.04.21.06.10.10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Apr 2015 06:10:11 -0700 (PDT) From: Linus Walleij To: u-boot@lists.denx.de, Albert Aribaud , Tom Rini , Simon Glass Date: Tue, 21 Apr 2015 15:10:06 +0200 Message-Id: <1429621806-29028-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 Cc: Steve Rae , u-boot-review@google.com Subject: [U-Boot] [PATCH] serial: pl01x: fix PL010 regression X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" commit aed2fbef5e9a0ab5a7cd01e742039a962f0b24ef "dm: serial: Tidy up the pl01x driver" caused a regression on (real hardware) PL010 by omitting to update the line control register when switching baudrate. Fix this by inlining the missing write to the baud control register. Also renaming the set_line_control() function to pl011_set_line_control() since this function is clearly PL011-specific, and it won't suffice to call that to set up line control. Tested on the Integrator/AP hardware. Cc: Simon Glass Signed-off-by: Linus Walleij --- drivers/serial/serial_pl01x.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 75eb6bd729e1..2124161734c0 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -95,7 +95,7 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs, return 0; } -static int set_line_control(struct pl01x_regs *regs) +static int pl011_set_line_control(struct pl01x_regs *regs) { unsigned int lcr; /* @@ -129,6 +129,9 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, case TYPE_PL010: { unsigned int divisor; + /* disable everything */ + writel(0, ®s->pl010_cr); + switch (baudrate) { case 9600: divisor = UART_PL010_BAUD_9600; @@ -152,6 +155,12 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); writel(divisor & 0xff, ®s->pl010_lcrl); + /* + * Set line control for the PL010 to be 8 bits, 1 stop bit, + * no parity, fifo enabled + */ + writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, + ®s->pl010_lcrh); /* Finally, enable the UART */ writel(UART_PL010_CR_UARTEN, ®s->pl010_cr); break; @@ -178,7 +187,7 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, writel(divider, ®s->pl011_ibrd); writel(fraction, ®s->pl011_fbrd); - set_line_control(regs); + pl011_set_line_control(regs); /* Finally, enable the UART */ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);