diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index 1f96498..8b9eaa0 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -11,9 +11,6 @@ config TARGET_MT_VENTOUX
 	bool "TeeJet Mt.Ventoux"
 	select SUPPORT_SPL
 
-config TARGET_OMAP3_SDP3430
-	bool "TI OMAP3430 SDP"
-
 config TARGET_OMAP3_BEAGLE
 	bool "TI OMAP3 BeagleBoard"
 	select SUPPORT_SPL
@@ -56,30 +53,17 @@ config TARGET_AM3517_CRANE
 	bool "am3517_crane"
 	select SUPPORT_SPL
 
-config TARGET_OMAP3_PANDORA
-	bool "OMAP3 Pandora"
-
 config TARGET_ECO5PK
 	bool "ECO5PK"
 	select SUPPORT_SPL
 
-config TARGET_DIG297
-	bool "DIG297"
-
 config TARGET_TRICORDER
 	bool "Tricorder"
 	select SUPPORT_SPL
 
-config TARGET_MCX
-	bool "MCX"
-	select SUPPORT_SPL
-
 config TARGET_OMAP3_LOGIC
 	bool "OMAP3 Logic"
 
-config TARGET_OMAP3_MVBLX
-	bool "OMAP3 MVBLX"
-
 config TARGET_NOKIA_RX51
 	bool "Nokia RX51"
 
@@ -111,7 +95,6 @@ config SYS_SOC
 
 source "board/logicpd/am3517evm/Kconfig"
 source "board/teejet/mt_ventoux/Kconfig"
-source "board/ti/sdp3430/Kconfig"
 source "board/ti/beagle/Kconfig"
 source "board/compulab/cm_t35/Kconfig"
 source "board/compulab/cm_t3517/Kconfig"
@@ -121,13 +104,9 @@ source "board/isee/igep00x0/Kconfig"
 source "board/overo/Kconfig"
 source "board/logicpd/zoom1/Kconfig"
 source "board/ti/am3517crane/Kconfig"
-source "board/pandora/Kconfig"
 source "board/8dtech/eco5pk/Kconfig"
-source "board/comelit/dig297/Kconfig"
 source "board/corscience/tricorder/Kconfig"
-source "board/htkw/mcx/Kconfig"
 source "board/logicpd/omap3som/Kconfig"
-source "board/matrix_vision/mvblx/Kconfig"
 source "board/nokia/rx51/Kconfig"
 source "board/technexion/tao3530/Kconfig"
 source "board/technexion/twister/Kconfig"
diff --git a/board/comelit/dig297/Kconfig b/board/comelit/dig297/Kconfig
deleted file mode 100644
index 6dccaff..0000000
--- a/board/comelit/dig297/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DIG297
-
-config SYS_BOARD
-	default "dig297"
-
-config SYS_VENDOR
-	default "comelit"
-
-config SYS_CONFIG_NAME
-	default "dig297"
-
-endif
diff --git a/board/comelit/dig297/MAINTAINERS b/board/comelit/dig297/MAINTAINERS
deleted file mode 100644
index 318374e..0000000
--- a/board/comelit/dig297/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DIG297 BOARD
-M:	Luca Ceresoli <luca.ceresoli@comelit.it>
-S:	Maintained
-F:	board/comelit/dig297/
-F:	include/configs/dig297.h
-F:	configs/dig297_defconfig
diff --git a/board/comelit/dig297/Makefile b/board/comelit/dig297/Makefile
deleted file mode 100644
index 1c85b63..0000000
--- a/board/comelit/dig297/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= dig297.o
diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c
deleted file mode 100644
index 9d4c41b..0000000
--- a/board/comelit/dig297/dig297.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * (C) Copyright 2011 Comelit Group SpA
- * Luca Ceresoli <luca.ceresoli@comelit.it>
- *
- * Based on board/ti/beagle/beagle.c:
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Sunil Kumar <sunilsaini05@gmail.com>
- *	Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/omap3-regs.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include "dig297.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_CMD_NET
-static void setup_net_chip(void);
-
-#define NET_LAN9221_RESET_GPIO 12
-
-/* GPMC CS 5 connected to an SMSC LAN9220 ethernet controller */
-#define NET_LAN9220_GPMC_CONFIG1	(DEVICESIZE_16BIT)
-#define NET_LAN9220_GPMC_CONFIG2	(CSWROFFTIME(8) | \
-					 CSRDOFFTIME(7) | \
-					 ADVONTIME(1))
-#define NET_LAN9220_GPMC_CONFIG3	(ADVWROFFTIME(2) | \
-					 ADVRDOFFTIME(2) | \
-					 ADVONTIME(1))
-#define NET_LAN9220_GPMC_CONFIG4	(WEOFFTIME(8) | \
-					 WEONTIME(1) |  \
-					 OEOFFTIME(7)|	\
-					 OEONTIME(1))
-#define NET_LAN9220_GPMC_CONFIG5	(PAGEBURSTACCESSTIME(0) | \
-					 RDACCESSTIME(6)        | \
-					 WRCYCLETIME(0x1D)      | \
-					 RDCYCLETIME(0x1D))
-#define NET_LAN9220_GPMC_CONFIG6	((1 << 31)          | \
-					 WRACCESSTIME(0x1D) | \
-					 WRDATAONADMUXBUS(3))
-
-static const u32 gpmc_lan_config[] = {
-	NET_LAN9220_GPMC_CONFIG1,
-	NET_LAN9220_GPMC_CONFIG2,
-	NET_LAN9220_GPMC_CONFIG3,
-	NET_LAN9220_GPMC_CONFIG4,
-	NET_LAN9220_GPMC_CONFIG5,
-	NET_LAN9220_GPMC_CONFIG6,
-	/* CONFIG7: computed by enable_gpmc_cs_config() */
-};
-#endif /* CONFIG_CMD_NET */
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init();		/* in SRAM or SDRAM, finish GPMC */
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
-	struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
-	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
-
-	twl4030_power_init();
-	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
-
-	/*
-	 * GPIO list
-	 * - 159 OUT (GPIO5+31): reset for remote camera interface connector.
-	 * - 19  OUT (GPIO1+19): integrated speaker amplifier (1=on, 0=shdn).
-	 * - 20  OUT (GPIO1+20): handset amplifier (1=on, 0=shdn).
-	 */
-
-	/* Configure GPIOs to output */
-	writel(~(GPIO19 | GPIO20), &gpio1_base->oe);
-	writel(~(GPIO31), &gpio5_base->oe);
-
-	/* Set GPIO values */
-	writel((GPIO19 | GPIO20), &gpio1_base->setdataout);
-	writel(0, &gpio5_base->setdataout);
-
-#if defined(CONFIG_CMD_NET)
-	setup_net_chip();
-#endif
-
-	dieid_num_r();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_DIG297();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
-	twl4030_power_mmc_init(0);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- *	      Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
-	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
-	/* Configure GPMC registers */
-	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
-			      CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-
-	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
-	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
-	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
-	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
-	       &ctrl_base->gpmc_nadv_ale);
-
-	/* Make GPIO 12 as output pin and send a magic pulse through it */
-	if (!gpio_request(NET_LAN9221_RESET_GPIO, "")) {
-		gpio_direction_output(NET_LAN9221_RESET_GPIO, 0);
-		gpio_set_value(NET_LAN9221_RESET_GPIO, 1);
-		udelay(1);
-		gpio_set_value(NET_LAN9221_RESET_GPIO, 0);
-		udelay(31000);	/* Should be >= 30ms according to datasheet */
-		gpio_set_value(NET_LAN9221_RESET_GPIO, 1);
-	}
-}
-#endif /* CONFIG_CMD_NET */
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-	return rc;
-}
diff --git a/board/comelit/dig297/dig297.h b/board/comelit/dig297/dig297.h
deleted file mode 100644
index 8edfc09..0000000
--- a/board/comelit/dig297/dig297.h
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- * (C) Copyright 2011 Comelit Group SpA
- * Luca Ceresoli <luca.ceresoli@comelit.it>
- *
- * Based on board/ti/beagle/beagle.h:
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _DIG297_H_
-#define _DIG297_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-	"OMAP3 DIG297 board",
-	"NAND",
-};
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_DIG297() \
-/*SDRC*/\
-	MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
-	MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
-	MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
-	MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
-	MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
-	MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
-	MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
-	MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
-	MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
-	MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
-	MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
-	MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
-	MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
-	MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
-	MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
-	MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
-	MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
-	MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
-	MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
-	MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
-	MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
-	MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
-	MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
-	MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
-	MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
-	MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
-	MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
-	MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
-	MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
-	MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
-	MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
-	MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
-	MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
-	MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
-	MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
-	MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
-	MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
-	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
-	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\
-/*GPMC*/\
-	MUX_VAL(CP(GPMC_A1),        (IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
-	MUX_VAL(CP(GPMC_A2),        (IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
-	MUX_VAL(CP(GPMC_A3),        (IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
-	MUX_VAL(CP(GPMC_A4),        (IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
-	MUX_VAL(CP(GPMC_A5),        (IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
-	MUX_VAL(CP(GPMC_A6),        (IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
-	MUX_VAL(CP(GPMC_A7),        (IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
-	MUX_VAL(CP(GPMC_A8),        (IDIS | PTU | EN  | M0)) /*GPMC_A8*/\
-	MUX_VAL(CP(GPMC_A9),        (IDIS | PTU | EN  | M0)) /*GPMC_A9*/\
-	MUX_VAL(CP(GPMC_A10),       (IDIS | PTU | EN  | M0)) /*GPMC_A10*/\
-	MUX_VAL(CP(GPMC_D0),        (IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
-	MUX_VAL(CP(GPMC_D1),        (IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
-	MUX_VAL(CP(GPMC_D2),        (IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
-	MUX_VAL(CP(GPMC_D3),        (IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
-	MUX_VAL(CP(GPMC_D4),        (IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
-	MUX_VAL(CP(GPMC_D5),        (IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
-	MUX_VAL(CP(GPMC_D6),        (IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
-	MUX_VAL(CP(GPMC_D7),        (IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
-	MUX_VAL(CP(GPMC_D8),        (IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
-	MUX_VAL(CP(GPMC_D9),        (IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
-	MUX_VAL(CP(GPMC_D10),       (IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
-	MUX_VAL(CP(GPMC_D11),       (IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
-	MUX_VAL(CP(GPMC_D12),       (IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
-	MUX_VAL(CP(GPMC_D13),       (IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
-	MUX_VAL(CP(GPMC_D14),       (IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
-	MUX_VAL(CP(GPMC_D15),       (IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
-	MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /*NAND*/\
-	/* GPMC_nCS1/2: not available on CUS package*/\
-	MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\
-	MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\
-	MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
-	MUX_VAL(CP(GPMC_NCS6),      (IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
-	MUX_VAL(CP(GPMC_NCS7),      (IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
-	MUX_VAL(CP(GPMC_NBE1),      (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\
-	/* GPMC_WAIT2: not available on CUS package*/\
-	MUX_VAL(CP(GPMC_WAIT3),     (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\
-	/* GPMC_CLK: NC (only asyncronous peripherals are connected) */\
-	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
-	MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
-	MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
-	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
-	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
-	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
-	/* GPMC_WAIT1: not available on CUS package*/\
-/*DSS*/\
-	MUX_VAL(CP(DSS_PCLK),       (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
-	MUX_VAL(CP(DSS_HSYNC),      (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
-	MUX_VAL(CP(DSS_VSYNC),      (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
-	/* DSS_ACBIAS: AC BIAS: connected to TFT, not to be driven */\
-	MUX_VAL(CP(DSS_ACBIAS),     (IDIS | PTU | EN  | M7))\
-	MUX_VAL(CP(DSS_DATA0),      (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
-	MUX_VAL(CP(DSS_DATA1),      (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
-	MUX_VAL(CP(DSS_DATA2),      (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
-	MUX_VAL(CP(DSS_DATA3),      (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
-	MUX_VAL(CP(DSS_DATA4),      (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
-	MUX_VAL(CP(DSS_DATA5),      (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
-	MUX_VAL(CP(DSS_DATA6),      (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
-	MUX_VAL(CP(DSS_DATA7),      (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
-	MUX_VAL(CP(DSS_DATA8),      (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
-	MUX_VAL(CP(DSS_DATA9),      (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
-	MUX_VAL(CP(DSS_DATA10),     (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
-	MUX_VAL(CP(DSS_DATA11),     (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
-	MUX_VAL(CP(DSS_DATA12),     (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
-	MUX_VAL(CP(DSS_DATA13),     (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
-	MUX_VAL(CP(DSS_DATA14),     (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
-	MUX_VAL(CP(DSS_DATA15),     (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
-	MUX_VAL(CP(DSS_DATA16),     (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
-	MUX_VAL(CP(DSS_DATA17),     (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
-	MUX_VAL(CP(DSS_DATA18),     (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
-	MUX_VAL(CP(DSS_DATA19),     (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
-	MUX_VAL(CP(DSS_DATA20),     (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
-	MUX_VAL(CP(DSS_DATA21),     (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
-	MUX_VAL(CP(DSS_DATA22),     (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
-	MUX_VAL(CP(DSS_DATA23),     (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
-/*CAMERA*/\
-	MUX_VAL(CP(CAM_HS),         (IEN  | PTU | EN  | M0)) /*CAM_HS */\
-	MUX_VAL(CP(CAM_VS),         (IEN  | PTU | EN  | M0)) /*CAM_VS */\
-	MUX_VAL(CP(CAM_XCLKA),      (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
-	MUX_VAL(CP(CAM_PCLK),       (IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
-	MUX_VAL(CP(CAM_FLD),        (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-	MUX_VAL(CP(CAM_D0),         (IEN  | PTD | DIS | M0)) /*CAM_D0*/\
-	MUX_VAL(CP(CAM_D1),         (IEN  | PTD | DIS | M0)) /*CAM_D1*/\
-	MUX_VAL(CP(CAM_D2),         (IEN  | PTD | DIS | M0)) /*CAM_D2*/\
-	MUX_VAL(CP(CAM_D3),         (IEN  | PTD | DIS | M0)) /*CAM_D3*/\
-	MUX_VAL(CP(CAM_D4),         (IEN  | PTD | DIS | M0)) /*CAM_D4*/\
-	MUX_VAL(CP(CAM_D5),         (IEN  | PTD | DIS | M0)) /*CAM_D5*/\
-	MUX_VAL(CP(CAM_D6),         (IEN  | PTD | DIS | M0)) /*CAM_D6*/\
-	MUX_VAL(CP(CAM_D7),         (IEN  | PTD | DIS | M0)) /*CAM_D7*/\
-	MUX_VAL(CP(CAM_D8),         (IEN  | PTD | DIS | M0)) /*CAM_D8*/\
-	MUX_VAL(CP(CAM_D9),         (IEN  | PTD | DIS | M0)) /*CAM_D9*/\
-	MUX_VAL(CP(CAM_D10),        (IEN  | PTD | DIS | M0)) /*CAM_D10*/\
-	MUX_VAL(CP(CAM_D11),        (IEN  | PTD | DIS | M0)) /*CAM_D11*/\
-	MUX_VAL(CP(CAM_XCLKB),      (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
-	MUX_VAL(CP(CAM_WEN),        (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(CAM_STROBE),     (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
-	MUX_VAL(CP(CSI2_DX0),       (IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
-	MUX_VAL(CP(CSI2_DY0),       (IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
-	MUX_VAL(CP(CSI2_DX1),       (IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
-	MUX_VAL(CP(CSI2_DY1),       (IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
-/*Audio Interface */\
-	MUX_VAL(CP(MCBSP2_FSX),     (IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
-	MUX_VAL(CP(MCBSP2_CLKX),    (IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
-	MUX_VAL(CP(MCBSP2_DR),      (IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
-	MUX_VAL(CP(MCBSP2_DX),      (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
-/*Expansion card */\
-	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
-	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
-	MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
-	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
-	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
-	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
-	MUX_VAL(CP(MMC1_DAT4),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
-	MUX_VAL(CP(MMC1_DAT5),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
-	MUX_VAL(CP(MMC1_DAT6),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
-	MUX_VAL(CP(MMC1_DAT7),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
-/*Wireless LAN */\
-	MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
-	MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
-	MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
-	MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
-	MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
-	MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
-	MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
-	MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
-	MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
-	MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
-/*Bluetooth*/\
-	MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
-	MUX_VAL(CP(MCBSP3_DR),      (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
-	MUX_VAL(CP(MCBSP3_CLKX),    (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
-	MUX_VAL(CP(MCBSP3_FSX),     (IEN  | PTD | DIS | M1)) /*UART2_RX*/\
-	MUX_VAL(CP(UART2_CTS),      (IEN  | PTD | DIS | M4)) /*GPIO_144*/\
-	MUX_VAL(CP(UART2_RTS),      (IEN  | PTD | DIS | M4)) /*GPIO_145*/\
-	MUX_VAL(CP(UART2_TX),       (IEN  | PTD | DIS | M4)) /*GPIO_146*/\
-	MUX_VAL(CP(UART2_RX),       (IEN  | PTD | DIS | M4)) /*GPIO_147*/\
-/*Modem Interface */\
-	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
-	MUX_VAL(CP(UART1_RTS),      (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
-	MUX_VAL(CP(UART1_CTS),      (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
-	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
-	MUX_VAL(CP(MCBSP4_CLKX),    (IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
-	MUX_VAL(CP(MCBSP4_DR),      (IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
-	MUX_VAL(CP(MCBSP4_DX),      (IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
-	MUX_VAL(CP(MCBSP4_FSX),     (IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
-	MUX_VAL(CP(MCBSP_CLKS),     (IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
-/*Serial Interface*/\
-	MUX_VAL(CP(UART3_CTS_RCTX), (IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
-	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
-	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
-	MUX_VAL(CP(HSUSB0_CLK),     (IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
-	MUX_VAL(CP(HSUSB0_STP),     (IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
-	MUX_VAL(CP(HSUSB0_DIR),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
-	MUX_VAL(CP(HSUSB0_NXT),     (IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
-	MUX_VAL(CP(HSUSB0_DATA0),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
-	MUX_VAL(CP(HSUSB0_DATA1),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
-	MUX_VAL(CP(HSUSB0_DATA2),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
-	MUX_VAL(CP(HSUSB0_DATA3),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
-	MUX_VAL(CP(HSUSB0_DATA4),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
-	MUX_VAL(CP(HSUSB0_DATA5),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
-	MUX_VAL(CP(HSUSB0_DATA6),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
-	MUX_VAL(CP(HSUSB0_DATA7),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
-	MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
-	MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
-	MUX_VAL(CP(I2C2_SCL),       (IEN  | PTU | EN  | M4)) /*GPIO_168*/\
-	MUX_VAL(CP(I2C2_SDA),       (IEN  | PTU | EN  | M4)) /*GPIO_183*/\
-	MUX_VAL(CP(I2C3_SCL),       (IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
-	MUX_VAL(CP(I2C3_SDA),       (IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
-	MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
-	MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
-/* USB EHCI (port 2) */\
-	MUX_VAL(CP(ETK_D14_ES2),    (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
-	MUX_VAL(CP(ETK_D15_ES2),    (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
-/* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\
-	/*
-	 * McSPI1_CLK.
-	 * IEN needed fot the McSPI to "receive" the clock and be able to
-	 * sample SOMI. See http://e2e.ti.com/support/arm174_microprocessors/
-	 * omap_applications_processors/f/42/p/29444/102394.aspx#102394
-	 */\
-	MUX_VAL(CP(MCSPI1_CLK),     (IEN  | PTD | EN  | M0))\
-	MUX_VAL(CP(MCSPI1_SIMO),    (IDIS | PTD | EN  | M0)) /*McSPI1_SIMO*/\
-	MUX_VAL(CP(MCSPI1_SOMI),    (IEN  | PTD | EN  | M0)) /*McSPI1_SOMI*/\
-	MUX_VAL(CP(MCSPI1_CS0),     (IDIS | PTU | EN  | M0)) /*McSPI1_CS0*/\
-/* MCSPI2: to HIMAX TFT controller.*/\
-	MUX_VAL(CP(MCSPI2_CLK),     (IDIS | PTD | EN  | M0)) /*MCSPI2_CLK*/\
-	MUX_VAL(CP(MCSPI2_SIMO),    (IDIS | PTD | EN  | M0)) /*MCSPI3_SIMO*/\
-	/* MCSPI3_SOMI: NC because HIMAX in monodirectional (no SOMI line) */\
-	MUX_VAL(CP(MCSPI2_SOMI),    (IDIS | PTU | DIS | M7))\
-	MUX_VAL(CP(MCSPI2_CS0),     (IDIS | PTU | EN  | M0)) /*MCSPI3_CS0*/\
-	MUX_VAL(CP(MCSPI2_CS1),     (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\
-/* GPIO */\
-	MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
-	MUX_VAL(CP(ETK_CLK_ES2),    (IDIS | PTU | EN  | M4)) /*GPIO_12*/\
-	MUX_VAL(CP(ETK_CTL_ES2),    (IEN  | PTU | EN  | M4)) /*GPIO_13*/\
-	MUX_VAL(CP(ETK_D0_ES2),     (IEN  | PTU | DIS | M4)) /*GPIO_14*/\
-	MUX_VAL(CP(ETK_D1_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_15*/\
-	MUX_VAL(CP(ETK_D2_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_16*/\
-	MUX_VAL(CP(ETK_D3_ES2),     (IEN  | PTU | DIS | M4)) /*GPIO_17*/\
-	MUX_VAL(CP(ETK_D4_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_18*/\
-	MUX_VAL(CP(ETK_D5_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_19*/\
-	MUX_VAL(CP(ETK_D6_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_20*/\
-	MUX_VAL(CP(ETK_D7_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_21*/\
-	MUX_VAL(CP(ETK_D9_ES2),     (IEN  | PTU | DIS | M4)) /*GPIO_23*/\
-	MUX_VAL(CP(ETK_D10_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_24*/\
-	MUX_VAL(CP(ETK_D11_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_25*/\
-	MUX_VAL(CP(ETK_D12_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_26*/\
-	MUX_VAL(CP(ETK_D13_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_27*/\
-	MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTD | DIS | M4)) /*GPIO_156*/\
-	MUX_VAL(CP(MCBSP1_FSR),     (IEN  | PTU | EN  | M4)) /*GPIO_157*/\
-	MUX_VAL(CP(MCBSP1_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_158*/\
-	MUX_VAL(CP(MCBSP1_DR),      (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
-	MUX_VAL(CP(MCBSP1_FSX),     (IEN  | PTD | DIS | M4)) /*GPIO_161*/\
-	MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_162*/\
-	MUX_VAL(CP(UART3_RTS_SD),   (IDIS | PTD | EN  | M4)) /*GPIO_164*/\
-	MUX_VAL(CP(HDQ_SIO),        (IDIS | PTU | DIS | M4)) /*GPIO_170*/\
-	MUX_VAL(CP(MCSPI1_CS3),     (IEN  | PTU | EN  | M4)) /*GPIO_177*/\
-/*Control and debug */\
-	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
-	MUX_VAL(CP(SYS_CLKREQ),     (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
-	MUX_VAL(CP(SYS_NIRQ),       (IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
-	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
-	MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /*GPIO_3*/\
-	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /*GPIO_4*/\
-	MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
-	MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
-	MUX_VAL(CP(SYS_BOOT6),      (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
-	MUX_VAL(CP(SYS_OFF_MODE),   (IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
-	MUX_VAL(CP(SYS_CLKOUT1),    (IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
-	MUX_VAL(CP(SYS_CLKOUT2),    (IEN  | PTU | EN  | M4)) /*GPIO_186*/\
-	MUX_VAL(CP(ETK_D8_ES2),     (IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
-	MUX_VAL(CP(D2D_MCAD1),      (IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
-	MUX_VAL(CP(D2D_MCAD2),      (IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
-	MUX_VAL(CP(D2D_MCAD3),      (IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
-	MUX_VAL(CP(D2D_MCAD4),      (IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
-	MUX_VAL(CP(D2D_MCAD5),      (IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
-	MUX_VAL(CP(D2D_MCAD6),      (IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
-	MUX_VAL(CP(D2D_MCAD7),      (IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
-	MUX_VAL(CP(D2D_MCAD8),      (IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
-	MUX_VAL(CP(D2D_MCAD9),      (IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
-	MUX_VAL(CP(D2D_MCAD10),     (IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
-	MUX_VAL(CP(D2D_MCAD11),     (IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
-	MUX_VAL(CP(D2D_MCAD12),     (IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
-	MUX_VAL(CP(D2D_MCAD13),     (IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
-	MUX_VAL(CP(D2D_MCAD14),     (IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
-	MUX_VAL(CP(D2D_MCAD15),     (IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
-	MUX_VAL(CP(D2D_MCAD16),     (IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
-	MUX_VAL(CP(D2D_MCAD17),     (IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
-	MUX_VAL(CP(D2D_MCAD18),     (IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
-	MUX_VAL(CP(D2D_MCAD19),     (IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
-	MUX_VAL(CP(D2D_MCAD20),     (IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
-	MUX_VAL(CP(D2D_MCAD21),     (IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
-	MUX_VAL(CP(D2D_MCAD22),     (IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
-	MUX_VAL(CP(D2D_MCAD23),     (IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
-	MUX_VAL(CP(D2D_MCAD24),     (IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
-	MUX_VAL(CP(D2D_MCAD25),     (IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
-	MUX_VAL(CP(D2D_MCAD26),     (IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
-	MUX_VAL(CP(D2D_MCAD27),     (IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
-	MUX_VAL(CP(D2D_MCAD28),     (IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
-	MUX_VAL(CP(D2D_MCAD29),     (IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
-	MUX_VAL(CP(D2D_MCAD30),     (IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
-	MUX_VAL(CP(D2D_MCAD31),     (IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
-	MUX_VAL(CP(D2D_MCAD32),     (IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
-	MUX_VAL(CP(D2D_MCAD33),     (IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
-	MUX_VAL(CP(D2D_MCAD34),     (IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
-	MUX_VAL(CP(D2D_MCAD35),     (IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
-	MUX_VAL(CP(D2D_MCAD36),     (IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
-	MUX_VAL(CP(D2D_CLK26MI),    (IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
-	MUX_VAL(CP(D2D_NRESPWRON),  (IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
-	MUX_VAL(CP(D2D_NRESWARM),   (IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
-	MUX_VAL(CP(D2D_ARM9NIRQ),   (IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
-	MUX_VAL(CP(D2D_UMA2P6FIQ),  (IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
-	MUX_VAL(CP(D2D_SPINT),      (IEN  | PTD | EN  | M0)) /*d2d_spint*/\
-	MUX_VAL(CP(D2D_FRINT),      (IEN  | PTD | EN  | M0)) /*d2d_frint*/\
-	MUX_VAL(CP(D2D_DMAREQ0),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
-	MUX_VAL(CP(D2D_DMAREQ1),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
-	MUX_VAL(CP(D2D_DMAREQ2),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
-	MUX_VAL(CP(D2D_DMAREQ3),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
-	MUX_VAL(CP(D2D_N3GTRST),    (IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
-	MUX_VAL(CP(D2D_N3GTDI),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
-	MUX_VAL(CP(D2D_N3GTDO),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
-	MUX_VAL(CP(D2D_N3GTMS),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
-	MUX_VAL(CP(D2D_N3GTCK),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
-	MUX_VAL(CP(D2D_N3GRTCK),    (IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
-	MUX_VAL(CP(D2D_MSTDBY),     (IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
-	MUX_VAL(CP(D2D_SWAKEUP),    (IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
-	MUX_VAL(CP(D2D_IDLEREQ),    (IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
-	MUX_VAL(CP(D2D_IDLEACK),    (IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
-	MUX_VAL(CP(D2D_MWRITE),     (IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
-	MUX_VAL(CP(D2D_SWRITE),     (IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
-	MUX_VAL(CP(D2D_MREAD),      (IEN  | PTD | DIS | M0)) /*d2d_mread*/\
-	MUX_VAL(CP(D2D_SREAD),      (IEN  | PTD | DIS | M0)) /*d2d_sread*/\
-	MUX_VAL(CP(D2D_MBUSFLAG),   (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
-	MUX_VAL(CP(D2D_SBUSFLAG),   (IEN  | PTD | DIS | M0)) /*d2d_sbusflag */
-
-#endif
diff --git a/board/htkw/mcx/Kconfig b/board/htkw/mcx/Kconfig
deleted file mode 100644
index 25ba548..0000000
--- a/board/htkw/mcx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MCX
-
-config SYS_BOARD
-	default "mcx"
-
-config SYS_VENDOR
-	default "htkw"
-
-config SYS_CONFIG_NAME
-	default "mcx"
-
-endif
diff --git a/board/htkw/mcx/MAINTAINERS b/board/htkw/mcx/MAINTAINERS
deleted file mode 100644
index c5f8873..0000000
--- a/board/htkw/mcx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MCX BOARD
-M:	Ilya Yanok <yanok@emcraft.com>
-S:	Maintained
-F:	board/htkw/mcx/
-F:	include/configs/mcx.h
-F:	configs/mcx_defconfig
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile
deleted file mode 100644
index 20149ba..0000000
--- a/board/htkw/mcx/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
-#
-# Based on ti/evm/Makefile
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mcx.o
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
deleted file mode 100644
index 4330cf0..0000000
--- a/board/htkw/mcx/mcx.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- *
- * Based on ti/evm/evm.c
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include <asm/gpio.h>
-#include <asm/omap_gpio.h>
-#include <asm/arch/dss.h>
-#include <asm/arch/clock.h>
-#include "errno.h"
-#include <i2c.h>
-#ifdef CONFIG_USB_EHCI
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-#include "mcx.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define HOT_WATER_BUTTON	42
-#define LCD_OUTPUT		55
-
-/* Address of the framebuffer in RAM. */
-#define FB_START_ADDRESS 0x88000000
-
-#ifdef CONFIG_USB_EHCI
-static struct omap_usbhs_board_data usbhs_bdata = {
-	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
-	return omap_ehci_hcd_stop();
-}
-#endif
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	gpio_direction_output(LCD_OUTPUT, 0);
-
-	return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-	if (gpio_request(HOT_WATER_BUTTON, "hot-water-button") < 0) {
-		puts("Failed to get hot-water-button pin\n");
-		return -ENODEV;
-	}
-	gpio_direction_input(HOT_WATER_BUTTON);
-
-	/*
-	 * if hot-water-button is pressed
-	 * change bootcmd
-	 */
-	if (gpio_get_value(HOT_WATER_BUTTON))
-		return 0;
-
-	setenv("bootcmd", "run swupdate");
-
-	return 0;
-}
-#endif
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_MCX();
-}
-
-#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
-
-static struct panel_config lcd_cfg = {
-	.timing_h       = PANEL_TIMING_H(40, 40, 48),
-	.timing_v       = PANEL_TIMING_V(29, 13, 3),
-	.pol_freq       = 0x00003000, /* Pol Freq */
-	.divisor        = 0x0001000E,
-	.panel_type     = 0x01, /* TFT */
-	.data_lines     = 0x03, /* 24 Bit RGB */
-	.load_mode      = 0x02, /* Frame Mode */
-	.panel_color	= 0,
-	.lcd_size	= PANEL_LCD_SIZE(800, 480),
-	.gfx_format	= GFXFORMAT_RGB24_UNPACKED,
-};
-
-int board_video_init(void)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	void *fb;
-
-	fb = (void *)FB_START_ADDRESS;
-
-	lcd_cfg.frame_buffer = fb;
-
-	setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
-	setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
-
-	omap3_dss_panel_config(&lcd_cfg);
-	omap3_dss_enable();
-
-	return 0;
-}
-#endif
diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h
deleted file mode 100644
index d6c5df2..0000000
--- a/board/htkw/mcx/mcx.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- *
- * Based on ti/evm/evm.h
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _AM3517EVM_H_
-#define _AM3517EVM_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_DISCRETE,
-	"HTKW mcx Board",
-	"NAND",
-};
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_MCX() \
-	/* SDRC */\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
-	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
-	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
-					/*sdrc_strben_dly0*/\
-	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
-					/*sdrc_strben_dly1*/\
-	/* GPMC */\
-	MUX_VAL(CP(GPMC_A1),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_A2),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_A3),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_A4),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_A5),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_A6),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_A7),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_A8),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_A9),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_A10),		(IEN | PTU | EN | M4)) \
-					/* GPIO_43 LCD buffer enable */ \
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS1),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_NCS2),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_NCS3),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_NCS4),		(IEN | PTU | EN  | M4))\
-	MUX_VAL(CP(GPMC_NCS5),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_NCS6),		(IEN | PTU | EN  | M4)) \
-					/* GPIO_57 TS_PenIRQn */\
-	MUX_VAL(CP(GPMC_NCS7),		(IEN | PTU | EN  | M4)) \
-					/* GPIO_58 ETHERNET RESET */\
-	MUX_VAL(CP(GPMC_CLK),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | DIS  | M4)) \
-					/* GPIO_61 SD-CARD CD */ \
-	MUX_VAL(CP(GPMC_NWP),		(IDIS  | PTU | EN | M4)) \
-			/* GPIO_62 Nand write protect, keep enabled */ \
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN | PTU | EN  | M4))\
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4))\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN | PTU | EN  | M4)) \
-					/* GPIO_65 SD-CARD WP */\
-	/* DSS */\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
-	/* CAMERA */\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(CAM_XCLKA),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(CAM_FLD),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_XCLKB),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CAM_STROBE),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | EN  | M4)) \
-	/* MMC */\
-	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
-	\
-	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(MMC2_CMD),		(IDIS | PTD | DIS | M4)) \
-					/* GPIO_131 LCD Enable */ \
-	MUX_VAL(CP(MMC2_DAT0),		(IDIS | PTD | DIS  | M4)) \
-					/* GPIO_132 USB host Enable */\
-	MUX_VAL(CP(MMC2_DAT1),		(IDIS  | PTD | DIS  | M4)) \
-					/* GPIO_133 HDMI PD */\
-	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4))\
-	/* McBSP */\
-	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
-	\
-	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTU | EN  | M4))\
-	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MCBSP2_DX),		(IEN  | PTU | EN  | M4))\
-	\
-	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTU | EN  | M4))\
-	\
-	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) \
-					/* GPIO_152 USB phy2 reset */\
-	MUX_VAL(CP(MCBSP4_DR),		(IEN | PTU | EN | M4)) \
-					/* GPIO_153 */\
-	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) \
-					/* GPIO_154 USB phy1 reset */\
-	MUX_VAL(CP(MCBSP4_FSX),		(IEN | PTU | EN | M4)) \
-					/* GPIO_155 TS_BUSY */\
-	/* UART */\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
-	\
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
-	\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
-	/* I2C */\
-	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M4)) \
-					/* GPIO_170 Touchscreen ISR */\
-	/* McSPI */\
-	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M3)) \
-					/* HSUSB2_dat7 */\
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M3)) \
-					/* HSUSB2_dat4 */\
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M3)) \
-					/* HSUSB2_dat5 */\
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | DIS | M3)) \
-					/* HSUSB2_dat6 */\
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | DIS | M3)) \
-					/* HSUSB2_dat3 */\
-	/* CCDC */\
-	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTD | EN  | M4)) \
-	/* CCDC_FIELD: gpio_95, uP-TXD4 */ \
-	MUX_VAL(CP(CCDC_FIELD),		(IDIS | PTD | DIS | M2)) \
-	/* CCDC_HD: gpio_96, uP-RTS4# */ \
-	MUX_VAL(CP(CCDC_HD),		(IDIS | PTD | DIS | M2)) \
-	/* CCDC_VD: gpio_97, uP-CTS4# */ \
-	MUX_VAL(CP(CCDC_VD),		(IEN  | PTD | EN  | M2)) \
-	/* CCDC_WEN: gpio_98, uP-RXD4 */ \
-	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M2)) \
-	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | EN  | M4)) \
-	/* RMII */\
-	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
-	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
-	MUX_VAL(CP(RMII_RXD0),		(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
-	/* HECC */\
-	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTD | EN  | M0)) \
-	/* HSUSB */\
-	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_STP),		(IEN  | PTU | DIS  | M0)) \
-	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
-	/* HDQ */\
-	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTD | EN  | M4)) \
-	/* Control and debug */\
-	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4))\
-	MUX_VAL(CP(SYS_BOOT6),		(IEN  | PTD | DIS | M4))\
-	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | DIS | M4)) \
-	\
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M4))\
-	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4))\
-	/* JTAG */\
-	MUX_VAL(CP(JTAG_NTRST),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(JTAG_TCK),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(JTAG_TMS),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(JTAG_TDI),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(JTAG_EMU0),		(IEN | PTU | EN  | M4)) \
-	MUX_VAL(CP(JTAG_EMU1),		(IEN | PTU | EN  | M4))\
-	/* ETK (ES2 onwards) */\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS  | PTD | DIS | M3)) \
-					/* hsusb1_stp */ \
-	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS  | PTD | DIS | M3)) \
-					/* hsusb1_clk */\
-	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | EN | M3)) \
-	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | EN | M3)) \
-	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN | M3)) \
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | EN | M3)) \
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | EN | M3)) \
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | EN | M3)) \
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | EN | M3)) \
-	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | EN | M3)) \
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | EN | M3)) \
-	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN | M3)) \
-	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M4)) \
-	/* Die to Die */\
-	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
-
-#endif
diff --git a/board/matrix_vision/mvblx/Kconfig b/board/matrix_vision/mvblx/Kconfig
deleted file mode 100644
index adbc20a..0000000
--- a/board/matrix_vision/mvblx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP3_MVBLX
-
-config SYS_BOARD
-	default "mvblx"
-
-config SYS_VENDOR
-	default "matrix_vision"
-
-config SYS_CONFIG_NAME
-	default "omap3_mvblx"
-
-endif
diff --git a/board/matrix_vision/mvblx/MAINTAINERS b/board/matrix_vision/mvblx/MAINTAINERS
deleted file mode 100644
index 2f9a153..0000000
--- a/board/matrix_vision/mvblx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MVBLX BOARD
-M:	Michael Jones <michael.jones@matrix-vision.de>
-S:	Maintained
-F:	board/matrix_vision/mvblx/
-F:	include/configs/omap3_mvblx.h
-F:	configs/omap3_mvblx_defconfig
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
deleted file mode 100644
index c056eba..0000000
--- a/board/matrix_vision/mvblx/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += mvblx.o fpga.o
-obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
-
-ccflags-y += -Werror
diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk
deleted file mode 100644
index de13072..0000000
--- a/board/matrix_vision/mvblx/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
-#
-# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
deleted file mode 100644
index 7f9b245..0000000
--- a/board/matrix_vision/mvblx/fpga.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2011
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include <asm/gpio.h>
-#include <linux/byteorder/generic.h>
-#include "fpga.h"
-
-#ifdef FPGA_DEBUG
-#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
-#else
-#define fpga_debug(fmt, args...)
-#endif
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
-	fpga_null_fn,   /* Altera_pre_fn */
-	fpga_config_fn,
-	fpga_status_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_null_fn,
-	fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
-	Altera_CYC2,
-	fast_passive_parallel,
-	Altera_EP3C5_SIZE,
-	(void *) &altera_fns,
-	NULL,
-	0
-};
-
-#define GPIO_RESET		43
-#define GPIO_DCLK		65
-#define GPIO_nSTATUS	157
-#define GPIO_CONF_DONE	158
-#define GPIO_nCONFIG	159
-#define GPIO_DATA0		54
-#define GPIO_DATA1		55
-#define GPIO_DATA2		56
-#define GPIO_DATA3		57
-#define GPIO_DATA4		58
-#define GPIO_DATA5		60
-#define GPIO_DATA6		61
-#define GPIO_DATA7		62
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* return FPGA_SUCCESS on success, else FPGA_FAIL
- */
-int mvblx_init_fpga(void)
-{
-	fpga_debug("Initializing FPGA interface\n");
-	fpga_init();
-	fpga_add(fpga_altera, &cyclone2);
-
-	if (gpio_request(GPIO_DCLK, "dclk") ||
-			gpio_request(GPIO_nSTATUS, "nStatus") ||
-#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
-			gpio_request(GPIO_CONF_DONE, "conf_done") ||
-#endif
-			gpio_request(GPIO_nCONFIG, "nConfig") ||
-			gpio_request(GPIO_DATA0, "data0") ||
-			gpio_request(GPIO_DATA1, "data1") ||
-			gpio_request(GPIO_DATA2, "data2") ||
-			gpio_request(GPIO_DATA3, "data3") ||
-			gpio_request(GPIO_DATA4, "data4") ||
-			gpio_request(GPIO_DATA5, "data5") ||
-			gpio_request(GPIO_DATA6, "data6") ||
-			gpio_request(GPIO_DATA7, "data7")) {
-		printf("%s: error requesting GPIOs.", __func__);
-		return FPGA_FAIL;
-	}
-
-	/* set up outputs */
-	gpio_direction_output(GPIO_DCLK,  0);
-	gpio_direction_output(GPIO_nCONFIG, 0);
-	gpio_direction_output(GPIO_DATA0, 0);
-	gpio_direction_output(GPIO_DATA1, 0);
-	gpio_direction_output(GPIO_DATA2, 0);
-	gpio_direction_output(GPIO_DATA3, 0);
-	gpio_direction_output(GPIO_DATA4, 0);
-	gpio_direction_output(GPIO_DATA5, 0);
-	gpio_direction_output(GPIO_DATA6, 0);
-	gpio_direction_output(GPIO_DATA7, 0);
-
-	/* NB omap_free_gpio() resets to an input, so we can't
-	 * free ie. nCONFIG, or else the FPGA would reset
-	 * Q: presumably gpio_free() has the same effect?
-	 */
-
-	/* set up inputs */
-	gpio_direction_input(GPIO_nSTATUS);
-#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
-	gpio_direction_input(GPIO_CONF_DONE);
-#endif
-
-	fpga_config_fn(0, 1, 0);
-	udelay(60);
-
-	return FPGA_SUCCESS;
-}
-
-int fpga_null_fn(int cookie)
-{
-	return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
-	fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
-	if (flush) {
-		gpio_set_value(GPIO_nCONFIG, !assert);
-		udelay(1);
-		gpio_set_value(GPIO_nCONFIG, assert);
-	}
-
-	return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
-	int result = 0;
-
-	/* since revA of BLX, we will not get this signal. */
-	udelay(10);
-#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
-	fpga_debug("not waiting for CONF_DONE.");
-	result = 1;
-#else
-	fpga_debug("CONF_DONE check ... ");
-	if (gpio_get_value(GPIO_CONF_DONE))  {
-		fpga_debug("high\n");
-		result = 1;
-	} else
-		fpga_debug("low\n");
-	gpio_free(GPIO_CONF_DONE);
-#endif
-
-	return result;
-}
-
-int fpga_status_fn(int cookie)
-{
-	int result = 0;
-	fpga_debug("STATUS check ... ");
-
-	result = gpio_get_value(GPIO_nSTATUS);
-
-	if (result < 0)
-		fpga_debug("error\n");
-	else if (result > 0)
-		fpga_debug("high\n");
-	else
-		fpga_debug("low\n");
-
-	return result;
-}
-
-static inline int _write_fpga(u8 byte)
-{
-	gpio_set_value(GPIO_DATA0, byte & 0x01);
-	gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
-	gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
-	gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
-	gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
-	gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
-	gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
-	gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
-
-	/* clock */
-	gpio_set_value(GPIO_DCLK, 1);
-	udelay(1);
-	gpio_set_value(GPIO_DCLK, 0);
-	udelay(1);
-
-	return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
-	unsigned char *data = (unsigned char *) buf;
-	int i;
-	int headerlen = len - cyclone2.size;
-
-	if (headerlen < 0)
-		return FPGA_FAIL;
-	else if (headerlen == sizeof(uint32_t)) {
-		const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */
-		char fpgavers_str[fpgavers_len];
-		snprintf(fpgavers_str, fpgavers_len, "0x%08x",
-				be32_to_cpup((uint32_t*)data));
-		setenv("fpgavers", fpgavers_str);
-	}
-
-	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
-	for (i = headerlen; i < len; i++)
-		_write_fpga(data[i]);
-	fpga_debug("-%s\n", __func__);
-
-	return FPGA_SUCCESS;
-}
diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h
deleted file mode 100644
index 411b039..0000000
--- a/board/matrix_vision/mvblx/fpga.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-extern int mvblx_init_fpga(void);
-
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
deleted file mode 100644
index c9d615b..0000000
--- a/board/matrix_vision/mvblx/mvblx.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * MATRIX VISION GmbH mvBlueLYNX-X
- *
- * Derived from Beagle and Overo
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Sunil Kumar <sunilsaini05@gmail.com>
- *	Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
-#include <asm/mach-types.h>
-#include "mvblx.h"
-#include "fpga.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET)
-static void setup_net_chip(void);
-#endif /* CONFIG_CMD_NET */
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init();	/* in SRAM or SDRAM, finish GPMC */
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
-	printf("mvBlueLYNX-X\n");
-	if (get_cpu_family() == CPU_OMAP36XX)
-		setenv("mpurate", "1000");
-	else
-		setenv("mpurate", "600");
-
-	twl4030_power_init();
-
-#if defined(CONFIG_CMD_NET)
-	setup_net_chip();
-#endif /* CONFIG_CMD_NET */
-
-	mvblx_init_fpga();
-
-	mac_read_from_eeprom();
-
-	dieid_num_r();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_MVBLX();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	omap_mmc_init(0, 0, 0, -1, -1);
-	omap_mmc_init(1, 0, 0, -1, -1);
-	return 0;
-}
-
-void board_mmc_power_init(void)
-{
-	twl4030_power_mmc_init(0);
-	twl4030_power_mmc_init(1);
-}
-#endif
-
-#if defined(CONFIG_CMD_NET)
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- *		Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
-	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
-	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
-	/* Configure GPMC registers */
-	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
-	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
-	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
-	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
-	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
-	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
-	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
-
-	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
-	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
-	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
-	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
-		&ctrl_base->gpmc_nadv_ale);
-
-	/* Make GPIO 139 as output pin */
-	writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
-
-	/* Now send a pulse on the GPIO pin */
-	writel(GPIO11, &gpio5_base->setdataout);
-	udelay(1);
-	writel(GPIO11, &gpio5_base->cleardataout);
-	udelay(1);
-	writel(GPIO11, &gpio5_base->setdataout);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-	return rc;
-}
-
-int overwrite_console(void)
-{
-	/* return true if console should be overwritten */
-	return 0;
-}
-
-#endif /* CONFIG_CMD_NET */
diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h
deleted file mode 100644
index 6c1c752..0000000
--- a/board/matrix_vision/mvblx/mvblx.h
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _MVBLX_H_
-#define _MVBLX_H_
-
-#include <asm/arch/sys_proto.h>
-
-const omap3_sysinfo sysinfo = {
-	DDR_DISCRETE,
-	"OMAP3 mvBlueLYNX-X camera",
-	"no NAND",
-};
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_MVBLX() \
- /*SDRC*/\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M4)) /*GPIO_41*/\
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M4)) /*GPIO_42*/\
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M4)) /*GPIO_43*/\
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
-	MUX_VAL(CP(GPMC_NCS3),		(IEN  | PTU | EN  | M4)) /*GPIO54*/\
-	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M4)) /*GPIO55*/\
-	MUX_VAL(CP(GPMC_NCS5),		(IEN  | PTU | EN  | M4)) /*GPIO56*/\
-	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTU | EN  | M4)) /*GPIO57*/\
-	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M4)) /*GPIO58*/\
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IEN  | PTU | EN  | M4)) /*GPIO60*/\
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M4)) /*GPIO61*/\
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTU | EN  | M4)) /*GPIO62*/\
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IDIS  | PTU | EN  | M4)) /*GPIO65*/\
- /*DSS*/\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M4)) /*not_used*/\
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
- /*CAMERA*/\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
-	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
-	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
-	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
-	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
-	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
-	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
- /*Audio Interface */\
-	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
-	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
-	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
-	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /*Expansion card 1*/\
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
-	MUX_VAL(CP(MMC1_DAT4),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
-	MUX_VAL(CP(MMC1_DAT5),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
-	MUX_VAL(CP(MMC1_DAT6),		(IDIS  | PTU | DIS  | M4)) /*GPIO_?*/\
-	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | DIS  | M7)) /*GPIO_129 disabled*/\
- /*Expansion card 2 */\
-	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | DIS  | M0)) /*MMC2_CLK*/\
-	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | DIS  | M0)) /*MMC2_CMD*/\
-	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT0*/\
-	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT1*/\
-	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT2*/\
-	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT3*/\
-	MUX_VAL(CP(MMC2_DAT4),		(IDIS  | PTU | DIS  | M4)) /*GPIO_136*/\
-	MUX_VAL(CP(MMC2_DAT5),		(IEN  | PTU | EN  | M4)) /*GPIO_137*/\
-	MUX_VAL(CP(MMC2_DAT6),		(IDIS  | PTU | DIS  | M4)) /*GPIO_138*/\
-	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M4)) /*GPIO_139*/\
- /*Bluetooth*/\
-	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
-	MUX_VAL(CP(MCBSP3_DR),		(IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
-	MUX_VAL(CP(MCBSP3_CLKX),	(IDIS | PTD | DIS | M1)) /*UART2_TX*/\
-	MUX_VAL(CP(MCBSP3_FSX),		(IDIS | PTD | DIS | M1)) /*UART2_RX*/\
- /*Modem Interface */\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
-	MUX_VAL(CP(UART1_CTS),		(IEN | PTU | EN | M4)) /*GPIO_150*/ \
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
-	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
-	MUX_VAL(CP(MCBSP1_FSR),		(IEN | PTU | EN  | M4)) /*GPIO_157*/\
-	MUX_VAL(CP(MCBSP1_DX),		(IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
-	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
-	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
-	MUX_VAL(CP(MCBSP1_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_161*/\
-	MUX_VAL(CP(MCBSP1_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_162*/\
- /*Serial Interface*/\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
-	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
-	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
-	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
-	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
-	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
-	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
-	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
-	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
-	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
-	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
-	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
-	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
-	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
-	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
-	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
-	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
-	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
-	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTU | EN  | M4)) /*GPIO_170*/\
-	MUX_VAL(CP(MCSPI1_CLK),		(IDIS  | PTU | DIS  | M4)) /*GPIO_171*/\
-	MUX_VAL(CP(MCSPI1_SIMO),	(IDIS  | PTU | DIS  | M4)) /*GPIO_172*/\
-	MUX_VAL(CP(MCSPI1_SOMI),	(IDIS  | PTU | DIS  | M4)) /*GPIO_173*/\
-	MUX_VAL(CP(MCSPI1_CS0),		(IDIS  | PTD | DIS  | M4)) /*GPIO_174*/\
-	MUX_VAL(CP(MCSPI1_CS3),		(IDIS  | PTU | DIS | M4)) /*GPIO_177*/\
- /* USB EHCI (port 2) not used */\
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI2_CLK*/\
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI2_SIMO*/\
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI2_SOMI*/\
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS0*/\
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS1*/\
- /*Control and debug */\
-	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
-	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
-	MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
-	MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M0)) /*GPIO_4*/\
-	MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
-	MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
-	MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
-	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
-	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS  | PTD | DIS | M4)) /*GPIO_10*/\
-	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTD | DIS  | M0)) /*SYS_CLKOUT2*/\
- /* USB EHCI (port 1) */\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
-	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
-	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
-	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
-	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
-	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
-	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
-	MUX_VAL(CP(ETK_D10_ES2),	(IEN | PTU | EN | M4)) /*GPIO_24*/\
-	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M4)) /*GPIO_25*/\
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_26*/\
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_27*/\
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_28*/\
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTU | DIS | M4)) /*GPIO_29*/\
- /*Die to Die */\
-	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
-	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
-	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
-	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
-	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
-	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
-	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
-	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
-	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
-	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
-	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
-	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
-	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
-	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
-	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
-	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
-	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
-	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
-	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
-	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
-	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
-	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
-	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
-	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
-	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
-	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
-	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
-	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
-	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
-	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
-	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
-	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
-	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
-	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
-	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
-	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
-	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
-	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
-	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
-	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
-	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
-	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
-	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
-	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
-	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
-	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
-	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
-	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
-	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
-	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
-	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
-	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
-	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
-	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
-	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
-	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
-	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
-	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
-	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
-	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
-	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
-	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
-	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
-	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
-	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
-
-#endif
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
deleted file mode 100644
index db42987..0000000
--- a/board/matrix_vision/mvblx/sys_eeprom.c
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
- * York Sun (yorksun@freescale.com)
- * Haiying Wang (haiying.wang@freescale.com)
- * Timur Tabi (timur@freescale.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-
-/* #define DEBUG */
-
-/*
- * static eeprom: EEPROM layout
- */
-static struct __attribute__ ((__packed__)) eeprom {
-	u8 id[16];		/* 0x01 - 0x0F Type e.g. 100wG-5111 */
-	u8 sn[10];		/* 0x10 - 0x19 Serial Number */
-	u8 date[6];		/* 0x1A - 0x1F Build Date */
-	u8 mac[6];		/* 0x20 - 0x25 MAC address  */
-	u8 reserved[10];/* 0x26 - 0x2f reserved */
-	u32 crc;        /* x+1         CRC32 checksum */
-} e;
-
-/* Set to 1 if we've read EEPROM into memory */
-static int has_been_read;
-
-/**
- * show_eeprom - display the contents of the EEPROM
- */
-static void show_eeprom(void)
-{
-	unsigned int crc;
-	char safe_string[16];
-
-#ifdef DEBUG
-	int i;
-#endif
-	u8 *p;
-
-	/* ID */
-	strncpy(safe_string, (char *)e.id, sizeof(e.id));
-	safe_string[sizeof(e.id)-1] = 0;
-	printf("ID: mvBlueLYNX-X%s\n", safe_string);
-
-	/* Serial number */
-	strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
-	safe_string[sizeof(e.sn)-1] = 0;
-	printf("SN: %s\n", safe_string);
-
-	/* Build date, BCD date values, as YYMMDDhhmmss */
-	printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
-		e.date[0], e.date[1], e.date[2],
-		e.date[3] & 0x7F, e.date[4], e.date[5],
-		e.date[3] & 0x80 ? "PM" : "");
-
-	/* Show MAC address  */
-	p = e.mac;
-	printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
-		p[0], p[1], p[2], p[3],	p[4], p[5]);
-
-	crc = crc32(0, (void *)&e, sizeof(e) - 4);
-
-	if (crc == be32_to_cpu(e.crc))
-		printf("CRC: %08x\n", be32_to_cpu(e.crc));
-	else
-		printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
-
-#ifdef DEBUG
-	printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
-	for (i = 0; i < sizeof(e); i++) {
-		if ((i % 16) == 0)
-			printf("%02X: ", i);
-		printf("%02X ", ((u8 *)&e)[i]);
-		if (((i % 16) == 15) || (i == sizeof(e) - 1))
-			printf("\n");
-	}
-#endif
-}
-
-/**
- * read_eeprom - read the EEPROM into memory
- */
-static int read_eeprom(void)
-{
-	int ret;
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	unsigned int bus;
-#endif
-
-	if (has_been_read)
-		return 0;
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	bus = i2c_get_bus_num();
-	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
-
-	ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
-		(uchar *)&e, sizeof(e));
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	i2c_set_bus_num(bus);
-#endif
-
-#ifdef DEBUG
-	show_eeprom();
-#endif
-
-	has_been_read = (ret == 0) ? 1 : 0;
-
-	return ret;
-}
-
-/**
- *  update_crc - update the CRC
- *
- *  This function should be called after each update to the EEPROM structure,
- *  to make sure the CRC is always correct.
- */
-static void update_crc(void)
-{
-	u32 crc;
-
-	crc = crc32(0, (void *)&e, sizeof(e) - 4);
-	e.crc = cpu_to_be32(crc);
-}
-
-/**
- * prog_eeprom - write the EEPROM from memory
- */
-static int prog_eeprom(void)
-{
-	int ret = 0;
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	unsigned int bus;
-#endif
-
-	update_crc();
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	bus = i2c_get_bus_num();
-	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
-
-	ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
-		(uchar *)&e, sizeof(e));
-
-	if (!ret) {
-		/* Verify the write by reading back the EEPROM and comparing */
-		struct eeprom e2;
-#ifdef DEBUG
-		printf("%s verifying...\n", __func__);
-#endif
-		ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
-			(uchar *)&e2, sizeof(e2));
-
-		if (!ret && memcmp(&e, &e2, sizeof(e)))
-			ret = -1;
-	}
-
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
-	i2c_set_bus_num(bus);
-#endif
-
-	if (ret) {
-		printf("Programming failed.\n");
-		has_been_read = 0;
-		return -1;
-	}
-
-	printf("Programming passed.\n");
-	return 0;
-}
-
-/**
- * h2i - converts hex character into a number
- *
- * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
- * the integer equivalent.
- */
-static inline u8 h2i(char p)
-{
-	if ((p >= '0') && (p <= '9'))
-		return p - '0';
-
-	if ((p >= 'A') && (p <= 'F'))
-		return (p - 'A') + 10;
-
-	if ((p >= 'a') && (p <= 'f'))
-		return (p - 'a') + 10;
-
-	return 0;
-}
-
-/**
- * set_date - stores the build date into the EEPROM
- *
- * This function takes a pointer to a string in the format "YYMMDDhhmmss"
- * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
- * and stores it in the build date field of the EEPROM local copy.
- */
-static void set_date(const char *string)
-{
-	unsigned int i;
-
-	if (strlen(string) != 12) {
-		printf("Usage: mac date YYMMDDhhmmss\n");
-		return;
-	}
-
-	for (i = 0; i < 6; i++)
-		e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
-
-	update_crc();
-}
-
-/**
- * set_mac_address - stores a MAC address into the EEPROM
- *
- * This function takes a pointer to MAC address string
- * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
- * stores it in the MAC address field in the EEPROM local copy.
- */
-static void set_mac_address(const char *string)
-{
-	char *p = (char *) string;
-	unsigned int i;
-
-	for (i = 0; *p && (i < 6); i++) {
-		e.mac[i] = simple_strtoul(p, &p, 16);
-		if (*p == ':')
-			p++;
-	}
-
-	update_crc();
-}
-
-int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	char cmd;
-
-	if (argc == 1) {
-		show_eeprom();
-		return 0;
-	}
-
-	cmd = argv[1][0];
-
-	if (cmd == 'r') {
-#ifdef DEBUG
-		printf("%s read\n", __func__);
-#endif
-		read_eeprom();
-		return 0;
-	}
-
-	if (argc == 2) {
-		switch (cmd) {
-		case 's':	/* save */
-#ifdef DEBUG
-			printf("%s save\n", __func__);
-#endif
-			prog_eeprom();
-			break;
-		default:
-			return cmd_usage(cmdtp);
-		}
-
-		return 0;
-	}
-
-	/* We know we have at least one parameter  */
-
-	switch (cmd) {
-	case 'n':	/* serial number */
-#ifdef DEBUG
-		printf("%s serial number\n", __func__);
-#endif
-		memset(e.sn, 0, sizeof(e.sn));
-		strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
-		update_crc();
-		break;
-	case 'd':	/* date BCD format YYMMDDhhmmss */
-		set_date(argv[2]);
-		break;
-	case 'e':	/* errata */
-		printf("mac errata not implemented\n");
-		break;
-	case 'i':	/* id */
-		memset(e.id, 0, sizeof(e.id));
-		strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
-		update_crc();
-		break;
-	case 'p':	/* ports */
-		printf("mac ports not implemented (always 1 port)\n");
-		break;
-	case '0' ... '9':
-		/* we only have "mac 0" but any digit can be used here */
-		set_mac_address(argv[2]);
-		break;
-	case 'h':	/* help */
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	return 0;
-}
-
-static inline int is_portrait(void)
-{
-	int i;
-	unsigned int orient_index = 0; /* idx of char which determines orientation */
-
-	for (i = sizeof(e.id)/sizeof(*e.id) - 1; i>=0; i--) {
-		if (e.id[i] == '-') {
-			orient_index = i+1;
-			break;
-		}
-	}
-
-	return (orient_index &&
-			(e.id[orient_index] >= '5') && (e.id[orient_index] <= '8'));
-}
-
-int mac_read_from_eeprom(void)
-{
-	u32 crc, crc_offset = offsetof(struct eeprom, crc);
-	u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
-#define FILENAME_LANDSCAPE "mvBlueLynx_X.rbf"
-#define FILENAME_PORTRAIT "mvBlueLynx_X_sensor_cd.rbf"
-
-	if (read_eeprom()) {
-		printf("EEPROM Read failed.\n");
-		return -1;
-	}
-
-	crc = crc32(0, (void *)&e, crc_offset);
-	crcp = (void *)&e + crc_offset;
-	if (crc != be32_to_cpu(*crcp)) {
-		printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
-			be32_to_cpu(e.crc));
-		return -1;
-	}
-
-	if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
-		memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
-		char ethaddr[18];
-
-		sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
-			e.mac[0],
-			e.mac[1],
-			e.mac[2],
-			e.mac[3],
-			e.mac[4],
-			e.mac[5]);
-		/* Only initialize environment variables that are blank
-		 * (i.e. have not yet been set)
-		 */
-		if (!getenv("ethaddr"))
-			setenv("ethaddr", ethaddr);
-	}
-
-	if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) &&
-		memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
-		char serial_num[12];
-
-		strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
-		/* Only initialize environment variables that are blank
-		 * (i.e. have not yet been set)
-		 */
-		if (!getenv("serial#"))
-			setenv("serial#", serial_num);
-	}
-
-	/* decide which fpga file to load depending on orientation */
-	if (is_portrait())
-		setenv("fpgafilename", FILENAME_PORTRAIT);
-	else
-		setenv("fpgafilename", FILENAME_LANDSCAPE);
-
-	/* TODO should I calculate CRC here? */
-	return 0;
-}
-
-#ifdef CONFIG_SERIAL_TAG
-void get_board_serial(struct tag_serialnr *serialnr)
-{
-	char *serial = getenv("serial#");
-
-	if (serial && (strlen(serial) > 3)) {
-		/* use the numerical part of the serial number LXnnnnnn */
-		serialnr->high = 0;
-		serialnr->low = simple_strtoul(serial + 2, NULL, 10);
-	} else {
-		serialnr->high = 0;
-		serialnr->low = 0;
-	}
-}
-#endif
diff --git a/board/pandora/Kconfig b/board/pandora/Kconfig
deleted file mode 100644
index 0b33818..0000000
--- a/board/pandora/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_OMAP3_PANDORA
-
-config SYS_BOARD
-	default "pandora"
-
-config SYS_CONFIG_NAME
-	default "omap3_pandora"
-
-endif
diff --git a/board/pandora/MAINTAINERS b/board/pandora/MAINTAINERS
deleted file mode 100644
index e123517..0000000
--- a/board/pandora/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PANDORA BOARD
-M:	Grazvydas Ignotas <notasas@gmail.com>
-S:	Maintained
-F:	board/pandora/
-F:	include/configs/omap3_pandora.h
-F:	configs/omap3_pandora_defconfig
diff --git a/board/pandora/Makefile b/board/pandora/Makefile
deleted file mode 100644
index 918b656..0000000
--- a/board/pandora/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= pandora.o
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
deleted file mode 100644
index 59b5a7e..0000000
--- a/board/pandora/pandora.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * (C) Copyright 2008
- * Grazvydas Ignotas <notasas@gmail.com>
- *
- * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- *	Sunil Kumar <sunilsaini05@gmail.com>
- *	Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "pandora.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TWL4030_BB_CFG_BBCHEN		(1 << 4)
-#define TWL4030_BB_CFG_BBSEL_3200MV	(3 << 2)
-#define TWL4030_BB_CFG_BBISEL_500UA	2
-
-#define CONTROL_WKUP_CTRL		0x48002a5c
-#define GPIO_IO_PWRDNZ			(1 << 6)
-#define PBIASLITEVMODE1			(1 << 8)
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-static void set_output_gpio(unsigned int gpio, int value)
-{
-	int ret;
-
-	ret = gpio_request(gpio, "");
-	if (ret != 0) {
-		printf("could not request GPIO %u\n", gpio);
-		return;
-	}
-	ret = gpio_direction_output(gpio, value);
-	if (ret != 0)
-		printf("could not set GPIO %u to %d\n", gpio, value);
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
-	t2_t *t2_base = (t2_t *)T2_BASE;
-	u32 pbias_lite;
-
-	twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
-
-	/* set up dual-voltage GPIOs to 1.8V */
-	pbias_lite = readl(&t2_base->pbias_lite);
-	pbias_lite &= ~PBIASLITEVMODE1;
-	pbias_lite |= PBIASLITEPWRDNZ1;
-	writel(pbias_lite, &t2_base->pbias_lite);
-	if (get_cpu_family() == CPU_OMAP36XX)
-		writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
-			CONTROL_WKUP_CTRL);
-
-	/* make sure audio and BT chips are in powerdown state */
-	set_output_gpio(14, 0);
-	set_output_gpio(15, 0);
-	set_output_gpio(118, 0);
-
-	/* enable USB supply */
-	set_output_gpio(164, 1);
-
-	/* wifi needs a short pulse to enter powersave state */
-	set_output_gpio(23, 1);
-	udelay(5000);
-	gpio_direction_output(23, 0);
-
-	/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
-	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
-		TWL4030_PM_RECEIVER_BB_CFG,
-		TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
-		TWL4030_BB_CFG_BBISEL_500UA);
-
-	dieid_num_r();
-
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_PANDORA();
-	if (get_cpu_family() == CPU_OMAP36XX) {
-		MUX_PANDORA_3730();
-	}
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
-	twl4030_power_mmc_init(0);
-}
-#endif
diff --git a/board/pandora/pandora.h b/board/pandora/pandora.h
deleted file mode 100644
index 268b929..0000000
--- a/board/pandora/pandora.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/*
- * (C) Copyright 2008
- * Grazvydas Ignotas <notasas@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _PANDORA_H_
-#define _PANDORA_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-	"OMAP3 Pandora",
-	"NAND",
-};
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN	- Pull type selection is active
- * M0	- Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_PANDORA() \
- /*SDRC*/\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
- /*DSS*/\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /*GPIO based game buttons*/\
-	MUX_VAL(CP(CAM_XCLKA),		(IEN  | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTD | DIS | M4)) /*GPIO_97 - L2*/\
-	MUX_VAL(CP(CAM_FLD),		(IEN  | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M4)) /*GPIO_99 - MENU*/\
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M4)) /*GPIO_100 - START*/\
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M4)) /*GPIO_101 - Y*/\
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M4)) /*GPIO_102 - L1*/\
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M4)) /*GPIO_105 - R1*/\
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M4)) /*GPIO_106 - B*/\
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M4)) /*GPIO_107 - R2*/\
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M4)) /*GPIO_109 - X*/\
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M4)) /*GPIO_110 - UP*/\
-	MUX_VAL(CP(CAM_XCLKB),		(IEN  | PTD | DIS | M4)) /*GPIO_111 - A*/\
- /*Audio Interface To External DAC (Headphone, Speakers)*/\
-	MUX_VAL(CP(MCBSP2_FSX),		(IDIS | PTD | DIS | M0)) /*McBSP2_FSX*/\
-	MUX_VAL(CP(MCBSP2_CLKX),	(IDIS | PTD | DIS | M0)) /*McBSP2_CLKX*/\
-	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
-	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTD | DIS | M0)) /*McBSP_CLKS*/\
-	MUX_VAL(CP(MCBSP2_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_118*/\
-								 /* - nPOWERDOWN_DAC*/\
- /*Expansion card 1*/\
-	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
-	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
- /*Expansion card 2*/\
-	MUX_VAL(CP(MMC2_CLK),		(IDIS | PTD | DIS | M0)) /*MMC2_CLK*/\
-	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
-	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
-	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
-	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
-	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
-	MUX_VAL(CP(MMC2_DAT4),		(IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT0*/\
-	MUX_VAL(CP(MMC2_DAT5),		(IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT1*/\
-	MUX_VAL(CP(MMC2_DAT6),		(IDIS | PTD | DIS | M1)) /*MMC2_DIR_CMD */\
-	MUX_VAL(CP(MMC2_DAT7),		(IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
-	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
- /*SDIO Interface to WIFI Module*/\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IEN  | PTD | DIS | M2)) /*MMC3_CLK*/\
-	MUX_VAL(CP(ETK_CTL_ES2),	(IEN  | PTU | EN  | M2)) /*MMC3_CMD*/\
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT0*/\
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT1*/\
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT2*/\
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | EN  | M2)) /*MMC3_DAT3*/\
- /*Audio Interface To Bluetooth chip*/\
-	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
-	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) /*McBSP3_DR*/\
-	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP3_CLKX*/\
-	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP3_FSX*/\
- /*Digital Interface to Bluetooth (UART)*/\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
-	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
-	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | EN  | M0)) /*UART1_CTS*/\
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
- /*Audio Interface to Triton2 chip (TPS65950)*/\
-	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP4_CLKX*/\
-	MUX_VAL(CP(MCBSP4_DR),		(IEN  | PTD | DIS | M0)) /*McBSP4_DR*/\
-	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M0)) /*McBSP4_DX*/\
-	MUX_VAL(CP(MCBSP4_FSX),		(IEN  | PTD | DIS | M0)) /*McBSP4_FSX*/\
- /*GPIO definitions for muxed pins on AV connector*/\
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTD | EN  | M4)) /*GPIO_144,*/\
-								 /*UART2_CTS*/\
-	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | EN  | M4)) /*GPIO_145,*/\
-								 /*UART2_RTS*/\
-	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | EN  | M4)) /*GPIO_146,*/\
-								 /*UART2_TX*/\
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | EN  | M4)) /*GPIO_147,*/\
-								 /*UART2_RX*/\
- /*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
- /*RX pulled up to avoid noise when nothing is connected to serial port*/\
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTU | EN  | M0)) /*UART3_RX*/\
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX*/\
- /*LEDs (Controlled by OMAP)*/\
-	MUX_VAL(CP(MMC1_DAT6),		(IDIS | PTD | DIS | M4)) /*GPIO_128*/\
-								 /* - LED_MMC1*/\
-	MUX_VAL(CP(MMC1_DAT7),		(IDIS | PTD | DIS | M4)) /*GPIO_129*/\
-								 /* - LED_MMC2*/\
-	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_158*/\
-								 /* - LED_BT*/\
-	MUX_VAL(CP(MCBSP1_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_159*/\
-								 /* - LED_WIFI*/\
- /*Switches*/\
-	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | DIS | M4)) /*GPIO_176*/\
-								 /* - nHOLD_SWITCH*/\
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M4)) /*GPIO_108*/\
-								 /* - nLID_SWITCH*/\
- /*External IRQs*/\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTD | DIS | M4)) /*GPIO_94*/\
-								 /* - nTOUCH_IRQ*/\
-	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M4)) /*GPIO_21*/\
-								 /* - WIFI_IRQ*/\
-	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M4)) /*GPIO_161*/\
-								 /* - nIRQ_NUB1*/\
-	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M4)) /*GPIO_162*/\
-								 /* - nIRQ_NUB2*/\
- /*Various other stuff*/\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTD | DIS | M4)) /*GPIO_163*/\
-								 /* - nOC_USB5*/\
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M4)) /*GPIO_22*/\
-								 /* - MSECURE*/\
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M4)) /*GPIO_115*/\
-								 /* - POP_OVERHEAT*/\
- /*External Resets and Enables*/\
-	MUX_VAL(CP(ETK_D0_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_14*/\
-								 /* - nHDPHN_SHUTDOWN*/\
-	MUX_VAL(CP(ETK_D1_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_15*/\
-								 /* - nBT_SHUTDOWN*/\
-	MUX_VAL(CP(ETK_D9_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_23*/\
-								 /* - nWIFI_RESET*/\
-	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | DIS | M4)) /*GPIO_157*/\
-								 /* - nLCD_RESET*/\
-	MUX_VAL(CP(MCBSP1_CLKR),	(IDIS | PTD | DIS | M4)) /*GPIO_156*/\
-								 /* - RESET_NUBS*/\
-	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M4)) /*GPIO_164*/\
-								 /* - EN_USB_5V*/\
- /*Spare GPIOs*/\
-	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTD | EN  | M4)) /*GPIO_58*/\
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTD | EN  | M4)) /*GPIO_64*/\
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTD | EN  | M4)) /*GPIO_65*/\
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M4)) /*GPIO_95*/\
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | EN  | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTD | EN  | M4)) /*GPIO_170*/\
- /*HS USB OTG Port (connects to HSUSB0)*/\
-	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
-	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
-	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
-	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
-	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
-	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
-	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
-	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
-	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
-	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
-	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- /*I2C Ports*/\
-	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL - T2_CTRL*/\
-	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA - T2_CTRL*/\
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL - NUBS*/\
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA - NUBS*/\
-	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL - T2_SR*/\
-	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA - T2_SR*/\
- /*Serial Interface (Touch, LCD control)*/\
-	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
-	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO*/\
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI*/\
-	MUX_VAL(CP(MCSPI1_CS0),		(IDIS | PTU | EN  | M0)) /*McSPI1_CS0 - TOUCH*/\
-	MUX_VAL(CP(MCSPI1_CS1),		(IDIS | PTU | EN  | M0)) /*McSPI1_CS1 - LCD*/\
- /*HS USB HOST Port (connects to HSUSB2)*/\
-	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)) /*USB_HOST_CLK*/\
-	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | EN  | M3)) /*USB_HOST_STP*/\
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_DIR*/\
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_NXT*/\
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D0*/\
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D1*/\
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D2*/\
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D3*/\
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D4*/\
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M3)) /*USB_HOST_D5*/\
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D6*/\
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M3)) /*USB_HOST_D7*/\
-	MUX_VAL(CP(ETK_D2_ES2),		(IDIS | PTD | DIS | M4)) /*GPIO_16*/\
-								 /* - nRESET_USB_HOST*/\
- /*Control and debug */\
-	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
-	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
-	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
-	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3*/\
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
-	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
-	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
-	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
-	MUX_VAL(CP(SYS_BOOT6),		(IEN  | PTD | DIS | M4)) /*GPIO_8*/\
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- /*JTAG*/\
-	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) /*JTAG_NTRST*/\
-	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /*JTAG_TCK*/\
-	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) /*JTAG_TMS*/\
-	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) /*JTAG_TDI*/\
-	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU0*/\
-	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/\
- /*Die to Die stuff*/\
-	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
-	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
-	MUX_VAL(CP(D2D_MCAD3),		(IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
-	MUX_VAL(CP(D2D_MCAD4),		(IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
-	MUX_VAL(CP(D2D_MCAD5),		(IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
-	MUX_VAL(CP(D2D_MCAD6),		(IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
-	MUX_VAL(CP(D2D_MCAD7),		(IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
-	MUX_VAL(CP(D2D_MCAD8),		(IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
-	MUX_VAL(CP(D2D_MCAD9),		(IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
-	MUX_VAL(CP(D2D_MCAD10),		(IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
-	MUX_VAL(CP(D2D_MCAD11),		(IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
-	MUX_VAL(CP(D2D_MCAD12),		(IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
-	MUX_VAL(CP(D2D_MCAD13),		(IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
-	MUX_VAL(CP(D2D_MCAD14),		(IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
-	MUX_VAL(CP(D2D_MCAD15),		(IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
-	MUX_VAL(CP(D2D_MCAD16),		(IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
-	MUX_VAL(CP(D2D_MCAD17),		(IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
-	MUX_VAL(CP(D2D_MCAD18),		(IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
-	MUX_VAL(CP(D2D_MCAD19),		(IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
-	MUX_VAL(CP(D2D_MCAD20),		(IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
-	MUX_VAL(CP(D2D_MCAD21),		(IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
-	MUX_VAL(CP(D2D_MCAD22),		(IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
-	MUX_VAL(CP(D2D_MCAD23),		(IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
-	MUX_VAL(CP(D2D_MCAD24),		(IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
-	MUX_VAL(CP(D2D_MCAD25),		(IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
-	MUX_VAL(CP(D2D_MCAD26),		(IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
-	MUX_VAL(CP(D2D_MCAD27),		(IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
-	MUX_VAL(CP(D2D_MCAD28),		(IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
-	MUX_VAL(CP(D2D_MCAD29),		(IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
-	MUX_VAL(CP(D2D_MCAD30),		(IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
-	MUX_VAL(CP(D2D_MCAD31),		(IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
-	MUX_VAL(CP(D2D_MCAD32),		(IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
-	MUX_VAL(CP(D2D_MCAD33),		(IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
-	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
-	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
-	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
-	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
-	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
-	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm*/\
-	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq*/\
-	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
-	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
-	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
-	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
-	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
-	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
-	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
-	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
-	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
-	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
-	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
-	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
-	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
-	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
-	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
-	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
-	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
-	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
-	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
-	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
-	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
-	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
-	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
-	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
-	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
-
-#define MUX_PANDORA_3730() \
-	MUX_VAL(CP(GPIO126),		(IEN  | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
-	MUX_VAL(CP(GPIO127),		(IEN  | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
-	MUX_VAL(CP(GPIO128),		(IDIS | PTD | DIS | M4)) /*GPIO_128 - LED_MMC1*/\
-	MUX_VAL(CP(GPIO129),		(IDIS | PTD | DIS | M4)) /*GPIO_129 - LED_MMC2*/
-
-#endif
diff --git a/board/ti/sdp3430/Kconfig b/board/ti/sdp3430/Kconfig
deleted file mode 100644
index 7e73d99..0000000
--- a/board/ti/sdp3430/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP3_SDP3430
-
-config SYS_BOARD
-	default "sdp3430"
-
-config SYS_VENDOR
-	default "ti"
-
-config SYS_CONFIG_NAME
-	default "omap3_sdp3430"
-
-endif
diff --git a/board/ti/sdp3430/MAINTAINERS b/board/ti/sdp3430/MAINTAINERS
deleted file mode 100644
index 943c196..0000000
--- a/board/ti/sdp3430/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SDP3430 BOARD
-M:	Nishanth Menon <nm@ti.com>
-S:	Maintained
-F:	board/ti/sdp3430/
-F:	include/configs/omap3_sdp3430.h
-F:	configs/omap3_sdp3430_defconfig
diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile
deleted file mode 100644
index 753f099..0000000
--- a/board/ti/sdp3430/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= sdp.o
diff --git a/board/ti/sdp3430/config.mk b/board/ti/sdp3430/config.mk
deleted file mode 100644
index e4d9be1..0000000
--- a/board/ti/sdp3430/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c
deleted file mode 100644
index 7171363..0000000
--- a/board/ti/sdp3430/sdp.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "sdp.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const omap3_sysinfo sysinfo = {
-	DDR_DISCRETE,
-	"OMAP3 SDP3430 board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-	"OneNAND",
-#elif defined(CONFIG_ENV_IS_IN_NAND)
-	"NAND",
-#else
-	"NOR",
-#endif
-};
-
-/* Timing definitions for GPMC controller for Sibley NOR */
-static const u32 gpmc_sdp_nor[] = {
-    SDP3430_NOR_GPMC_CONF1,
-    SDP3430_NOR_GPMC_CONF2,
-    SDP3430_NOR_GPMC_CONF3,
-    SDP3430_NOR_GPMC_CONF4,
-    SDP3430_NOR_GPMC_CONF5,
-    SDP3430_NOR_GPMC_CONF6,
-    /*CONF7- computed as params */
-};
-
-/*
- * Timing definitions for GPMC controller for Debug Board
- * Debug board contains access to ethernet and DIP Switch setting
- * information etc.
- */
-static const u32 gpmc_sdp_debug[] = {
-    SDP3430_DEBUG_GPMC_CONF1,
-    SDP3430_DEBUG_GPMC_CONF2,
-    SDP3430_DEBUG_GPMC_CONF3,
-    SDP3430_DEBUG_GPMC_CONF4,
-    SDP3430_DEBUG_GPMC_CONF5,
-    SDP3430_DEBUG_GPMC_CONF6,
-    /*CONF7- computed as params */
-};
-
-/* Timing defintions for GPMC OneNAND */
-static const u32 gpmc_sdp_onenand[] = {
-    SDP3430_ONENAND_GPMC_CONF1,
-    SDP3430_ONENAND_GPMC_CONF2,
-    SDP3430_ONENAND_GPMC_CONF3,
-    SDP3430_ONENAND_GPMC_CONF4,
-    SDP3430_ONENAND_GPMC_CONF5,
-    SDP3430_ONENAND_GPMC_CONF6,
-    /*CONF7- computed as params */
-};
-
-/* GPMC definitions for GPMC NAND */
-static const u32 gpmc_sdp_nand[] = {
-    SDP3430_NAND_GPMC_CONF1,
-    SDP3430_NAND_GPMC_CONF2,
-    SDP3430_NAND_GPMC_CONF3,
-    SDP3430_NAND_GPMC_CONF4,
-    SDP3430_NAND_GPMC_CONF5,
-    SDP3430_NAND_GPMC_CONF6,
-    /*CONF7- computed as params */
-};
-
-/* gpmc_cfg is initialized by gpmc_init and we use it here */
-extern struct gpmc *gpmc_cfg;
-
-/**
- * @brief board_init - gpmc and basic setup as phase1 of boot sequence
- *
- * @return 0
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* TODO: Dynamically pop out CS mapping and program accordingly */
-	/* Configure devices for default ON ON ON settings */
-	enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
-			CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
-	enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
-			GPMC_SIZE_16M);
-	enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
-			GPMC_SIZE_16M);
-	enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
-			GPMC_SIZE_16M);
-	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	return 0;
-}
-
-#define LAN_RESET_REGISTER	(CONFIG_LAN91C96_BASE + 0x01c)
-#define ETH_CONTROL_REG		(CONFIG_LAN91C96_BASE + 0x30b)
-
-/**
- * @brief board_eth_init Take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete.
- */
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_LAN91C96
-	int cnt = 20;
-
-	writew(0x0, LAN_RESET_REGISTER);
-	do {
-		writew(0x1, LAN_RESET_REGISTER);
-		udelay(100);
-		if (cnt == 0)
-			goto reset_err_out;
-		--cnt;
-	} while (readw(LAN_RESET_REGISTER) != 0x1);
-
-	cnt = 20;
-
-	do {
-		writew(0x0, LAN_RESET_REGISTER);
-		udelay(100);
-		if (cnt == 0)
-			goto reset_err_out;
-		--cnt;
-	} while (readw(LAN_RESET_REGISTER) != 0x0000);
-	udelay(1000);
-
-	writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
-	udelay(1000);
-	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-reset_err_out:
-
-#endif
-	return rc;
-}
-
-/**
- * @brief misc_init_r - Configure SDP board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
-	/* Partial setup:
-	 *   VAUX3 - 2.8V for DVI
-	 *   VPLL1 - 1.8V
-	 *   VDAC  - 1.8V
-	 * and turns on LEDA/LEDB (not needed ... NOP?)
-	 */
-	twl4030_power_init();
-
-	/* FIXME finish setup:
-	 *   VAUX1 - 2.8V for mainboard I/O
-	 *   VAUX2 - 2.8V for camera
-	 *   VAUX4 - 1.8V for OMAP3 CSI
-	 *   VMMC1 - 3.15V (init, variable) for MMC1
-	 *   VMMC2 - 1.85V for MMC2
-	 *   VSIM  - off (init, variable) for MMC1.DAT[3..7], SIM
-	 *   VPLL2 - 1.8V
-	 */
-
-	return 0;
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the hardware. Many pins need to be moved from protect
- * to primary mode.
- */
-void set_muxconf_regs(void)
-{
-	/* platform specific muxes */
-	MUX_SDP3430();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
-	twl4030_power_mmc_init(0);
-}
-#endif
diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h
deleted file mode 100644
index 0e63189..0000000
--- a/board/ti/sdp3430/sdp.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _BOARD_SDP_H_
-#define _BOARD_SDP_H_
-
-#define OFF_IN_PD	0
-#define OFF_OUT_PD	0
-
-/*
- * IEN	- Input Enable
- * IDIS	- Input Disable
- * PTD	- Pull type Down
- * PTU	- Pull type Up
- * DIS	- Pull type selection is inactive
- * EN	- Pull type selection is active
- * M0	- Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_SDP3430()\
-	/*SDRC*/\
-	MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
-	/*GPMC*/\
-	MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
-	MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
-	MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
-	MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
-	MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\
-	MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\
-	MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\
-	MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\
-	MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\
-	MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\
-	MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\
-	/*DSS*/\
-	MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	/*CAMERA*/\
-	MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\
-	MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\
-	MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\
-	MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	/*Audio InterfACe */\
-	MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	/*Expansion Card */\
-	MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
-	MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	/*Wireless LAN */\
-	MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\
-	MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\
-	MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\
-	MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\
-	/*Bluetooth*/\
-	MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	/*Modem Interface */\
-	MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
-	MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\
-	MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\
-	MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\
-	MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\
-	MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\
-	MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
-	MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	/*Serial Interface*/\
-	MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
-	MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	/* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\
-	MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
-	MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
-	MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
-	MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
-	MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
-	MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
-	MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\
-	MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\
-	MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\
-	MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\
-	MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	/*Control and debug */\
-	MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\
-	MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\
-	MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\
-	MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\
-	MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\
-	MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\
-	MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\
-	MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
-	MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
-	MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\
-	MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\
-	MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\
-	MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\
-	MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	/*Die to Die */\
-	MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
-	MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\
-	MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
-	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\
-	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/
-
-/*
- * GPMC Timing definitions for SDP3430
- * at L3 = 166Mhz
- */
-
-/* Timing definitions for GPMC controller for Sibley NOR */
-#define SDP3430_NOR_GPMC_CONF1 0x00001200
-#define SDP3430_NOR_GPMC_CONF2 0x001F1F00
-#define SDP3430_NOR_GPMC_CONF3 0x00080802
-#define SDP3430_NOR_GPMC_CONF4 0x1C091C09
-#define SDP3430_NOR_GPMC_CONF5 0x01131F1F
-#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2
-
-/*
- * Timing definitions for GPMC controller for Debug Board
- * Debug board contains access to ethernet and DIP Switch setting
- * information etc.
- */
-#define SDP3430_DEBUG_GPMC_CONF1 0x00611200
-#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01
-#define SDP3430_DEBUG_GPMC_CONF3 0x00080803
-#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09
-#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F
-#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4
-
-/* Timing defintions for GPMC OneNAND */
-#define SDP3430_ONENAND_GPMC_CONF1 0x00001200
-#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01
-#define SDP3430_ONENAND_GPMC_CONF3 0x00030301
-#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04
-#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010
-#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000
-
-/* GPMC definitions for GPMC NAND */
-#define SDP3430_NAND_GPMC_CONF1 0x00000800
-#define SDP3430_NAND_GPMC_CONF2 0x00141400
-#define SDP3430_NAND_GPMC_CONF3 0x00141400
-#define SDP3430_NAND_GPMC_CONF4 0x0F010F01
-#define SDP3430_NAND_GPMC_CONF5 0x010C1414
-#define SDP3430_NAND_GPMC_CONF6 0x1F040A80
-
-#endif /* _BOARD_SDP_H_ */
diff --git a/configs/dig297_defconfig b/configs/dig297_defconfig
deleted file mode 100644
index 0d18290..0000000
--- a/configs/dig297_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_DIG297=y
-CONFIG_DM=n
-CONFIG_DM_SERIAL=n
-CONFIG_DM_GPIO=n
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
deleted file mode 100644
index 2f61858..0000000
--- a/configs/mcx_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_SPL=y
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_MCX=y
-CONFIG_DM=n
-CONFIG_DM_SERIAL=n
-CONFIG_DM_GPIO=n
diff --git a/configs/omap3_mvblx_defconfig b/configs/omap3_mvblx_defconfig
deleted file mode 100644
index b75f513..0000000
--- a/configs/omap3_mvblx_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_MVBLX=y
-CONFIG_DM=n
-CONFIG_DM_SERIAL=n
-CONFIG_DM_GPIO=n
diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig
deleted file mode 100644
index dd0f17c..0000000
--- a/configs/omap3_pandora_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_PANDORA=y
-CONFIG_DM=n
-CONFIG_DM_SERIAL=n
-CONFIG_DM_GPIO=n
diff --git a/configs/omap3_sdp3430_defconfig b/configs/omap3_sdp3430_defconfig
deleted file mode 100644
index b3a8745..0000000
--- a/configs/omap3_sdp3430_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_SDP3430=y
-CONFIG_DM=n
-CONFIG_DM_SERIAL=n
-CONFIG_DM_GPIO=n
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 95a2362..e3e0be7 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,11 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+sdp3430          arm         armv7          -           -           Nishanth Menon <nm@ti.com>
+pandora          arm         armv7          -           -           Grazvydas Ignotas <notasas@gmail.com>
+dig297           arm         armv7          -           -           Luca Ceresoli <luca.ceresoli@comelit.it>
+mcx              arm         armv7          -           -           Ilya Yanok <yanok@emcraft.com>
+mvblx            arm         armv7          -           -           Michael Jones <michael.jones@matrix-vision.de>
 cam_enc_4xx      arm         arm926ejs      -           -           Heiko Schocher <hs@denx.de>
 dm355evm         arm         arm926ejs      -           -           Sandeep Paulraj <s-paulraj@ti.com>
 dm355leopard     arm         arm926ejs      -           -           Sandeep Paulraj <s-paulraj@ti.com>
diff --git a/include/configs/dig297.h b/include/configs/dig297.h
deleted file mode 100644
index 9326401..0000000
--- a/include/configs/dig297.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * (C) Copyright 2011 Comelit Group SpA
- * Luca Ceresoli <luca.ceresoli@comelit.it>
- *
- * Based on omap3_beagle.h:
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * Configuration settings for the Comelit DIG297 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/mach-types.h>
-#ifdef MACH_TYPE_OMAP3_CPS
-#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
-#else
-#define MACH_TYPE_OMAP3_CPS 2751
-#endif
-#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP		/* in a TI OMAP core */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-
-#define CONFIG_SYS_TEXT_BASE	0x80008000
-
-#define CONFIG_SDRC	/* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-						/* Sector */
-#define CONFIG_SYS_MALLOC_LEN		(1024 << 10) /* UBI needs >= 512 kB */
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/*
- * select serial console configuration: UART3 (ttyO2)
- */
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
-#define CONFIG_SERIAL3			3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_DOS_PARTITION
-
-/* library portions to compile in */
-#define CONFIG_RBTREE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_LZO
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_UBI		/* UBI Support			*/
-#define CONFIG_CMD_UBIFS	/* UBIFS Support		*/
-#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands    */
-#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
-#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:896k(uboot),"\
-				"128k(uboot-env),3m(kernel),252m(ubi)"
-
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_NAND		/* NAND support			*/
-
-#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
-#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
-#undef CONFIG_CMD_IMI		/* iminfo			*/
-#undef CONFIG_CMD_IMLS		/* List all found images	*/
-#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
-#undef CONFIG_CMD_NFS		/* NFS support			*/
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER
-#define CONFIG_TWL4030_LED
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT	16
-#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
-							/* to access nand */
-#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
-							/* to access nand at */
-							/* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
-
-#if defined(CONFIG_CMD_NET)
-/*
- * SMSC9220 Ethernet
- */
-
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SMC911X_BASE     0x2C000000
-
-#endif /* (CONFIG_CMD_NET) */
-
-/* Environment information */
-#define CONFIG_BOOTDELAY		1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=0x82000000\0" \
-	"console=ttyO2,115200n8\0" \
-	"mtdids=" MTDIDS_DEFAULT "\0" \
-	"mtdparts=" MTDPARTS_DEFAULT "\0" \
-	"partition=nand0,3\0"\
-	"mmcroot=/dev/mmcblk0p2 rw\0" \
-	"mmcrootfstype=ext3 rootwait\0" \
-	"nandroot=ubi0:rootfs ro\0" \
-	"nandrootfstype=ubifs\0" \
-	"nfspath=/srv/nfs\0" \
-	"tftpfilename=uImage\0" \
-	"gatewayip=0.0.0.0\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"${mtdparts} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype} " \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
-			"${netmask}:${hostname}::off\0" \
-	"nandargs=setenv bootargs console=${console} " \
-		"${mtdparts} " \
-		"ubi.mtd=3 " \
-		"root=${nandroot} " \
-		"rootfstype=${nandrootfstype} " \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
-			"${netmask}:${hostname}::off\0" \
-	"netargs=setenv bootargs console=${console} " \
-		"${mtdparts} " \
-		"root=/dev/nfs rw " \
-		"nfsroot=${serverip}:${nfspath} " \
-		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
-			"${netmask}:${hostname}::off\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"bootm ${loadaddr}\0" \
-	"nandboot=echo Booting from nand ...; " \
-		"run nandargs; " \
-		"nand read ${loadaddr} 100000 300000; " \
-		"bootm ${loadaddr}\0" \
-	"netboot=echo Booting from network ...; " \
-		"run netargs; " \
-		"tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
-		"bootm ${loadaddr}\0" \
-	"resetenv=nand erase e0000 20000\0"\
-
-#define CONFIG_BOOTCOMMAND \
-	"run nandboot"
-
-#define CONFIG_AUTO_COMPLETE
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"DIG297# "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
-								/* works on */
-#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
-					0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
-							/* load address */
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
-#define CONFIG_SYS_FLASH_BASE		boot_flash_base
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_ENV_IS_IN_NAND
-#define SMNAND_ENV_OFFSET		0x0E0000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
deleted file mode 100644
index 3fd3184..0000000
--- a/include/configs/mcx.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- *
- * Based on omap3_evm_config.h
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP			/* in a TI OMAP core */
-#define CONFIG_OMAP3_MCX		/* working with mcx */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define MACH_TYPE_MCX			3656
-#define CONFIG_MACH_TYPE	MACH_TYPE_MCX
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
-#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
-
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap.h>
-
-#define CONFIG_OF_LIBFDT
-#define CONFIG_FIT
-
-/*
- * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
- * and older u-boot.bin with the new U-Boot SPL.
- */
-#define CONFIG_SYS_TEXT_BASE		0x80008000
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
-#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
-/*
- * DDR related
- */
-#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
-#define CONFIG_SERIAL3			3	/* UART3 */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-#define CONFIG_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
-
-/* EHCI */
-#define CONFIG_USB_STORAGE
-#define CONFIG_OMAP3_GPIO_2
-#define CONFIG_OMAP3_GPIO_5
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_OMAP
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	57
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_NAND		/* NAND support			*/
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_GPIO
-
-#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
-#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
-#undef CONFIG_CMD_IMI		/* iminfo			*/
-#undef CONFIG_CMD_IMLS		/* List all found images	*/
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/* RTC */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68
-
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
-							/* to access nand */
-#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
-							/* to access */
-							/* nand at CS0 */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
-							/* NAND devices */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV		"nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET	0x680000
-#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
-
-/* Environment information */
-#define CONFIG_BOOTDELAY	3
-
-#define CONFIG_BOOTFILE		"uImage"
-
-/* Setup MTD for NAND on the SOM */
-#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO),"	\
-				"1m(u-boot),256k(env1),"		\
-				"256k(env2),6m(kernel),6m(k_recovery),"	\
-				"8m(fs_recovery),-(common_data)"
-
-#define CONFIG_HOSTNAME mcx
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0"	\
-	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0"	\
-	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
-	"addfb=setenv bootargs ${bootargs} vram=6M "			\
-		"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0"	\
-	"addip_sta=setenv bootargs ${bootargs} "			\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
-		"${netmask}:${hostname}:eth0:off\0"			\
-	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
-	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
-		"else run addip_sta;fi\0"				\
-	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consoledev},${baudrate}\0"			\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"baudrate=115200\0"						\
-	"consoledev=ttyO2\0"						\
-	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
-	"loadaddr=0x82000000\0"						\
-	"load=tftp ${loadaddr} ${u-boot}\0"				\
-	"load_k=tftp ${loadaddr} ${bootfile}\0"				\
-	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0"			\
-	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
-	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
-	"mmcargs=root=/dev/mmcblk0p2 rw "				\
-		"rootfstype=ext3 rootwait\0"				\
-	"mmcboot=echo Booting from mmc ...; "				\
-		"run mmcargs; "						\
-		"run addip addtty addmtd addfb addeth addmisc;"		\
-		"run loaduimage; "					\
-		"bootm ${loadaddr}\0"					\
-	"net_nfs=run load_k; "						\
-		"run nfsargs; "						\
-		"run addip addtty addmtd addfb addeth addmisc;"		\
-		"bootm ${loadaddr}\0"					\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
-	"uboot_addr=0x80000\0"						\
-	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
-		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
-	"updatemlo=nandecc hw;nand erase 0 20000;"			\
-		"nand write ${loadaddr} 0 20000\0"			\
-	"upd=if run load;then echo Updating u-boot;if run update;"	\
-		"then echo U-Boot updated;"				\
-			"else echo Error updating u-boot !;"		\
-			"echo Board without bootloader !!;"		\
-		"fi;"							\
-		"else echo U-Boot not downloaded..exiting;fi\0"		\
-	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0"		\
-	"bootscript=echo Running bootscript from mmc ...; "		\
-		"source ${loadaddr}\0"					\
-	"nandargs=setenv bootargs ubi.mtd=7 "				\
-		"root=ubi0:rootfs rootfstype=ubifs\0"			\
-	"nandboot=echo Booting from nand ...; "				\
-		"run nandargs; "					\
-		"ubi part nand0,4;"					\
-		"ubi readvol ${loadaddr} kernel;"			\
-		"run addtty addmtd addfb addeth addmisc;"		\
-		"bootm ${loadaddr}\0"					\
-	"preboot=ubi part nand0,7;"					\
-		"ubi readvol ${loadaddr} splash;"			\
-		"bmp display ${loadaddr};"				\
-		"gpio set 55\0"						\
-	"swupdate_args=setenv bootargs root=/dev/ram "			\
-		"quiet loglevel=1 "					\
-		"consoleblank=0 ${swupdate_misc}\0"			\
-	"swupdate=echo Running Sw-Update...;"				\
-		"if printenv mtdparts;then echo Starting SwUpdate...; "	\
-		"else mtdparts default;fi; "				\
-		"ubi part nand0,5;"					\
-		"ubi readvol 0x82000000 kernel_recovery;"		\
-		"ubi part nand0,6;"					\
-		"ubi readvol 0x84000000 fs_recovery;"			\
-		"run swupdate_args; "					\
-		"setenv bootargs ${bootargs} "				\
-			"${mtdparts} "					\
-			"vram=6M omapfb.vram=1:2M,2:2M,3:2M "		\
-			"omapdss.def_disp=lcd;"				\
-		"bootm 0x82000000 0x84000000\0"				\
-	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;"	\
-		"then source 82000000;else run nandboot;fi\0"
-
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-
-/*
- * Miscellaneous configurable options
- */
-#define V_PROMPT			"mcx # "
-
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		V_PROMPT
-#define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command */
-						/* args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
-					0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
-								/* address */
-#define CONFIG_PREBOOT
-
-/*
- * AM3517 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-/*
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_ENV_IS_IN_NAND
-#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
-
-/* Redundant Environment */
-#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
-						2 * CONFIG_SYS_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
-					CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS	1
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-/* Defines for SPL */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NAND_SIMPLE
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
-
-#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
-#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-
-/* move malloc and bss high to prevent clashing with the main image */
-#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
-#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_PAGE_COUNT	64
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
-#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
-					 48, 49, 50, 51, 52, 53, 54, 55,\
-					 56, 57, 58, 59, 60, 61, 62, 63}
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
-#define CONFIG_SPL_NAND_SOFTECC
-
-#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-
-/*
- * ethernet support
- *
- */
-#if defined(CONFIG_CMD_NET)
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#endif
-
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_CMD_BMP
-#define CONFIG_VIDEO_OMAP3
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
deleted file mode 100644
index b61297f..0000000
--- a/include/configs/omap3_mvblx.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * MATRIX VISION GmbH mvBlueLYNX-X
- *
- * Derived from omap3_beagle.h:
- * (C) Copyright 2006-2008
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * Configuration settings for the TI OMAP3530 Beagle board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_MVBLX		1	/* working with mvBlueLYNX-X */
-#define CONFIG_MACH_TYPE	MACH_TYPE_MVBLX
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define CONFIG_SDRC	/* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_OF_LIBFDT		1
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-#define CONFIG_SERIAL_TAG		1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE			(2 << 10)	/* 2 KiB */
-						/* Sector */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
-#define CONFIG_SERIAL1			1	/* UART1 */
-
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_DOS_PARTITION		1
-
-/* silent console by default */
-#define CONFIG_SYS_DEVICE_NULLDEV	1
-#define CONFIG_SILENT_CONSOLE		1
-
-/* USB */
-#define CONFIG_MUSB_UDC			1
-#define CONFIG_USB_OMAP3		1
-#define CONFIG_TWL4030_USB		1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE		1
-#define CONFIG_USB_TTY			1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
-#define CONFIG_USBD_VENDORID			0x164c
-#define CONFIG_USBD_PRODUCTID_GSERIAL	0x0201
-#define CONFIG_USBD_PRODUCTID_CDCACM	0x0201
-#define CONFIG_USBD_MANUFACTURER		"MATRIX VISION GmbH"
-#define CONFIG_USBD_PRODUCT_NAME		"mvBlueLYNX-X"
-
-/* no FLASH available */
-#define CONFIG_SYS_NO_FLASH
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IMI		/* iminfo			*/
-#undef CONFIG_CMD_IMLS		/* List all found images	*/
-#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
-#define CONFIG_CMD_NFS		/* NFS support			*/
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER		1
-
-/* Environment information */
-#undef CONFIG_ENV_OVERWRITE	/* disallow overwriting serial# and ethaddr */
-#define CONFIG_BOOTDELAY		0
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR "S"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"silent=true\0" \
-	"loadaddr=0x82000000\0" \
-	"usbtty=cdc_acm\0" \
-	"console=ttyO0,115200n8\0" \
-	"mpurate=600\0" \
-	"vram=12M\0" \
-	"dvimode=1024x768-24@60\0" \
-	"defaultdisplay=dvi\0" \
-	"loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\
-		"/lib/firmware/mvblx/${fpgafilename}; then " \
-			"fpga load 0 ${loadaddr} ${filesize}; " \
-		"fi;\0" \
-	"mmcdev=0\0" \
-	"mmcroot=/dev/mmcblk0p2 rw\0" \
-	"mmcrootfstype=ext3 rootwait\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"mpurate=${mpurate} " \
-		"vram=${vram} " \
-		"omapfb.mode=dvi:${dvimode} " \
-		"omapfb.debug=y " \
-		"omapdss.def_disp=${defaultdisplay} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype} " \
-		"mvfw.fpgavers=${fpgavers} " \
-		"${cmdline_suffix}\0" \
-	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
-	"importbootenv=echo Importing environment from mmc ...; " \
-		"env import -t $loadaddr $filesize\0" \
-	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"bootm ${loadaddr}\0" \
-	"mmcbootcmd= " \
-		"echo Trying mmc${mmcdev}; " \
-		"mmc dev ${mmcdev}; " \
-		"if mmc rescan; then " \
-			"setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
-			"echo SD/MMC found on device ${mmcdev};" \
-			"if run loadbootenv; then " \
-			   "echo Loading boot environment from mmc${mmcdev}; " \
-			   "run importbootenv; " \
-			"fi;" \
-			"run loadfpga; " \
-			"if test -n $uenvcmd; then " \
-				"echo Running uenvcmd ...;" \
-				"run uenvcmd;" \
-			"fi;" \
-			"if run loaduimage; then " \
-				"run mmcboot; " \
-			"fi;" \
-		"fi\0"
-
-#define CONFIG_BOOTCOMMAND \
-	"setenv mmcdev 1;" \
-	"run mmcbootcmd || " \
-	"setenv mmcdev 0;" \
-	"run mmcbootcmd"
-
-
-#define CONFIG_AUTO_COMPLETE		1
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"mvblx # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_ALT_MEMTEST      1 /* alternative memtest with looping */
-#define CONFIG_SYS_MEMTEST_START	(0x82000000)	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		(0x9dffffff)	/* end = 448 MB */
-#define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)    /* dummy address */
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-#define CONFIG_ENV_IS_NOWHERE	1
-
-/*----------------------------------------------------------------------------
- * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
- *----------------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NET)
-  #define CONFIG_SMC911X		1
-  #define CONFIG_SMC911X_32_BIT
-  #define CONFIG_SMC911X_BASE     0x2C000000
-#endif /* (CONFIG_CMD_NET) */
-
-#define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_CYCLON2
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4  /* 2^4 = 16-byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_EEPROM_BUS_NUM	2
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_OMAP3_SPI
-
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
deleted file mode 100644
index 11d7b86..0000000
--- a/include/configs/omap3_pandora.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * (C) Copyright 2008-2010
- * Gražvydas Ignotas <notasas@gmail.com>
- *
- * Configuration settings for the OMAP3 Pandora.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP3_PANDORA	1	/* working with pandora */
-#define CONFIG_OMAP_GPIO
-#define CONFIG_OMAP_COMMON
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define CONFIG_SDRC	/* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h>	/* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-#define CONFIG_OF_LIBFDT		1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 + CONFIG_ENV_SIZE)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
-#define CONFIG_SYS_DEVICE_NULLDEV	1
-
-/* USB */
-#define CONFIG_MUSB_UDC			1
-#define CONFIG_USB_OMAP3		1
-#define CONFIG_TWL4030_USB		1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE		1
-#define CONFIG_USB_TTY			1
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
-#define CONFIG_SERIAL3			3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
-					115200}
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_DOS_PARTITION		1
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
-
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_NAND		/* NAND support			*/
-#define CONFIG_CMD_CACHE	/* Cache control		*/
-
-#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
-#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
-#undef CONFIG_CMD_IMI		/* iminfo			*/
-#undef CONFIG_CMD_IMLS		/* List all found images	*/
-#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
-#undef CONFIG_CMD_NFS		/* NFS support			*/
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER		1
-#define CONFIG_TWL4030_LED		1
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_NAND_OMAP_GPMC
-#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
-							/* to access nand */
-#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
-							/* to access nand */
-							/* at CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
-						/* devices */
-
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
-#define MTDIDS_DEFAULT			"nand0=nand"
-#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(xloader),"\
-					"1920k(uboot),128k(uboot-env),"\
-					"10m(boot),-(rootfs)"
-#else
-#define MTDPARTS_DEFAULT
-#endif
-
-/* Environment information */
-#define CONFIG_BOOTDELAY		1
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"usbtty=cdc_acm\0" \
-	"loadaddr=0x82000000\0" \
-	"bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
-		"rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \
-	"mtdparts=" MTDPARTS_DEFAULT "\0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"if mmc rescan && fatload mmc1 0 ${loadaddr} autoboot.scr || " \
-			"ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \
-		"source ${loadaddr}; " \
-	"fi; " \
-	"ubi part boot && ubifsmount ubi:boot && " \
-		"ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
-
-#define CONFIG_AUTO_COMPLETE	1
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"Pandora # "
-#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command */
-						/* args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
-					0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
-								/* address */
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-#define CONFIG_SYS_TEXT_BASE		0x80008000
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					CONFIG_SYS_INIT_RAM_SIZE - \
-					GENERATED_GBL_DATA_SIZE)
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		NAND_BASE
-#endif
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_ENV_IS_IN_NAND		1
-#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
-
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
-#endif				/* __CONFIG_H */
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
deleted file mode 100644
index 1ca79d4..0000000
--- a/include/configs/omap3_sdp3430.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- * (C) Copyright 2006-2009
- * Texas Instruments Incorporated.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- * Nishanth Menon <nm@ti.com>
- *
- * Configuration settings for the 3430 TI SDP3430 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* TODO: REMOVE THE FOLLOWING
- * Retained the following till size.h is removed in u-boot
- */
-#include <linux/sizes.h>
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */
-#define CONFIG_OMAP_COMMON
-/* Common ARM Erratas */
-#define CONFIG_ARM_ERRATA_454179
-#define CONFIG_ARM_ERRATA_430973
-#define CONFIG_ARM_ERRATA_621766
-
-#define CONFIG_SDRC	/* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/*
- * NOTE:  these #defines presume standard SDP jumper settings.
- * In particular:
- *  - 26 MHz clock (not 19.2 or 38.4 MHz)
- *  - Boot from 128MB NOR, not NAND or OneNAND
- *
- * At this writing, OMAP3 U-Boot support doesn't permit concurrent
- * support for all the flash types the board supports.
- */
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-#define CONFIG_OF_LIBFDT		1
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 256k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE			(256 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * Hardware drivers
- */
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER		1
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
- * swapped with UART2 via jumpering.  Downsides of using J8:  it doesn't
- * support UART boot (that's only for UART3); it prevents sharing a Linux
- * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
- *
- * UART boot uses UART3 on J9, and the SDP user's guide says to use
- * that for console.  Downsides of using J9:  you can't use IRDA too;
- * since UART3 isn't in the CORE power domain, it may be a bit less
- * usable in certain PM-sensitive debug scenarios.
- */
-#undef CONSOLE_J9			/* else J8/UART1 (innermost) */
-
-#ifdef CONSOLE_J9
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
-#define CONFIG_SERIAL3			3	/* UART3 */
-#else
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
-#define CONFIG_SERIAL1			1	/* UART1 */
-#endif
-
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-
-/*
- * I2C for power management setup
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
-#define CONFIG_SYS_I2C_OMAP34XX
-
-/* OMITTED:  single 1 Gbit MT29F1G NAND flash */
-
-/*
- * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
- */
-#define CONFIG_SYS_FLASH_BASE		0x10000000
-#define CONFIG_FLASH_CFI_DRIVER		1	/* Use drivers/cfi_flash.c */
-#define CONFIG_SYS_FLASH_CFI		1	/* use CFI geometry data */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* ~10x faster writes */
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware sector protection */
-#define CONFIG_SYS_FLASH_EMPTY_INFO	1	/* flinfo 'E' for empty */
-#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS      1	/* max number of flash banks */
-
-#define CONFIG_SYS_FLASH_CFI_WIDTH	2
-#define PHYS_FLASH_SIZE			(128 << 20)
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors on one chip */
-
-/* OMITTED:  single 2 Gbit KFM2G16 OneNAND flash */
-
-#define CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_SYS_ENV_SECT_SIZE	(256 << 10)
-#define CONFIG_ENV_OFFSET		CONFIG_SYS_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
-/*--------------------------------------------------------------------------*/
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_DHCP		/* DHCP Support			*/
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_NET
-
-/* Disabled commands */
-#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
-#undef CONFIG_CMD_IMLS		/* List all found images	*/
-
-/*--------------------------------------------------------------------------*/
-/*
- * MMC boot support
- */
-
-#if defined(CONFIG_CMD_MMC)
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_DOS_PARTITION		1
-#endif
-
-/*----------------------------------------------------------------------------
- * SMSC9115 Ethernet from SMSC9118 family
- *----------------------------------------------------------------------------
- */
-#if defined(CONFIG_CMD_NET)
-
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE	DEBUG_BASE
-#define CONFIG_LAN91C96_EXT_PHY
-
-#define CONFIG_BOOTP_SEND_HOSTNAME
-/*
- * BOOTP fields
- */
-#define CONFIG_BOOTP_SUBNETMASK		0x00000001
-#define CONFIG_BOOTP_GATEWAY		0x00000002
-#define CONFIG_BOOTP_HOSTNAME		0x00000004
-#define CONFIG_BOOTP_BOOTPATH		0x00000010
-#endif /* (CONFIG_CMD_NET) */
-
-/*
- * Environment setup
- *
- * Default boot order:  mmc bootscript, MMC uImage, NOR image.
- * Network booting environment must be configured at site.
- */
-
-/* allow overwriting serial config and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=0x82000000\0" \
-	"console=ttyS0,115200n8\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"root=/dev/mmcblk0p2 rw " \
-		"rootfstype=ext3 rootwait\0" \
-	"norargs=setenv bootargs console=${console} " \
-		"root=/dev/mtdblock3 rw " \
-		"rootfstype=jffs2\0" \
-	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from MMC/SD ...; " \
-		"autoscr ${loadaddr}\0" \
-	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
-	"mmcboot=echo Booting from MMC/SD ...; " \
-		"run mmcargs; " \
-		"bootm ${loadaddr}\0" \
-	"norboot=echo Booting from NOR ...; " \
-		"run norargs; " \
-		"bootm 0x80000\0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"if mmcinit; then " \
-		"if run loadbootscript; then " \
-			"run bootscript; " \
-		"else " \
-			"if run loaduimage; then " \
-				"run mmcboot; " \
-			"else run norboot; " \
-			"fi; " \
-		"fi; " \
-	"else run norboot; fi"
-
-#define CONFIG_AUTO_COMPLETE		1
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"OMAP34XX SDP # "
-#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-
-/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
- * a basic sanity check ONLY
- * IF you would like to increase coverage, increase the end address
- * or run the test with custom options
- */
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x01000000)
-#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
- * 32KHz clk, or from external sig. This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-/*
- * SDRAM Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * NOR FLASH usage ... default nCS0:
- *  - one 256KB sector for U-Boot
- *  - one 256KB sector for its parameters (not all used)
- *  - eight sectors (2 MB) for kernel
- *  - rest for JFFS2
- */
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
-
-/*
- * NAND FLASH usage ... default nCS1:
- *  - four 128KB sectors for X-Loader
- *  - four 128KB sectors for U-Boot
- *  - two 128KB sector for its parameters
- *  - 32 sectors (4 MB) for kernel
- *  - rest for filesystem
- */
-
-/*
- * OneNAND FLASH usage ... default nCS2:
- *  - four 128KB sectors for X-Loader
- *  - two 128KB sectors for U-Boot
- *  - one 128KB sector for its parameters
- *  - sixteen sectors (2 MB) for kernel
- *  - rest for filesystem
- */
-
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
-#endif				/* __CONFIG_H */
