diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 6827721..2780cd8 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -17,37 +17,9 @@ config TARGET_DA850EVM
 	bool "DA850 EVM board"
 	select SUPPORT_SPL
 
-config TARGET_CAM_ENC_4XX
-	bool "CAM ENC 4xx board"
-	select SUPPORT_SPL
-
-config TARGET_DAVINCI_DM355EVM
-	bool "DM355 EVM board"
-
-config TARGET_DAVINCI_DM355LEOPARD
-	bool "DM355 Leopard board"
-
-config TARGET_DAVINCI_DM365EVM
-	bool "DM365 EVM board"
-
-config TARGET_DAVINCI_DM6467EVM
-	bool "DM6467 EVM board"
-
-config TARGET_DAVINCI_DVEVM
-	bool "DVEVM board"
-
 config TARGET_EA20
 	bool "EA20 board"
 
-config TARGET_DAVINCI_SCHMOOGIE
-	bool "Schmoogie board"
-
-config TARGET_DAVINCI_SFFSDR
-	bool "SFFSDR board"
-
-config TARGET_DAVINCI_SONATA
-	bool "Sonata board"
-
 config TARGET_CALIMAIN
 	bool "Calimain board"
 
@@ -57,18 +29,9 @@ config SYS_SOC
 	default "davinci"
 
 source "board/enbw/enbw_cmc/Kconfig"
-source "board/ait/cam_enc_4xx/Kconfig"
 source "board/Barix/ipam390/Kconfig"
 source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/dm355evm/Kconfig"
-source "board/davinci/dm355leopard/Kconfig"
-source "board/davinci/dm365evm/Kconfig"
-source "board/davinci/dm6467evm/Kconfig"
-source "board/davinci/dvevm/Kconfig"
 source "board/davinci/ea20/Kconfig"
-source "board/davinci/schmoogie/Kconfig"
-source "board/davinci/sffsdr/Kconfig"
-source "board/davinci/sonata/Kconfig"
 source "board/omicron/calimain/Kconfig"
 
 endif
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 7d67191..2ec7a46 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -9,17 +9,12 @@
 
 obj-y				+= cpu.o misc.o timer.o psc.o pinmux.o reset.o
 obj-$(CONFIG_DA850_LOWLEVEL)	+= da850_lowlevel.o
-obj-$(CONFIG_SOC_DM355)	+= dm355.o
-obj-$(CONFIG_SOC_DM365)	+= dm365.o
-obj-$(CONFIG_SOC_DM644X)	+= dm644x.o
-obj-$(CONFIG_SOC_DM646X)	+= dm646x.o
 obj-$(CONFIG_SOC_DA830)	+= da830_pinmux.o
 obj-$(CONFIG_SOC_DA850)	+= da850_pinmux.o
 obj-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_FRAMEWORK)	+= spl.o
-obj-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
 obj-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
 endif
 
diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index ff61147..d7429c8 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
@@ -30,24 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define BIT(x)		(1 << (x))
 
-/* SOC-specific pll info */
-#ifdef CONFIG_SOC_DM355
-#define ARM_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DM644X
-#define ARM_PLLDIV	PLLC_PLLDIV2
-#define DSP_PLLDIV	PLLC_PLLDIV1
-#define DDR_PLLDIV	PLLC_PLLDIV2
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DSP_PLLDIV	PLLC_PLLDIV1
-#define ARM_PLLDIV	PLLC_PLLDIV2
-#define DDR_PLLDIV	PLLC_PLLDIV1
-#endif
-
 #ifdef CONFIG_SOC_DA8XX
 unsigned int sysdiv[9] = {
 	PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
@@ -125,46 +107,23 @@ static unsigned pll_div(volatile void *pllbase, unsigned offset)
 
 static inline unsigned pll_prediv(volatile void *pllbase)
 {
-#ifdef CONFIG_SOC_DM355
-	/* this register read seems to fail on pll0 */
-	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-		return 8;
-	else
-		return pll_div(pllbase, PLLC_PREDIV);
-#elif defined(CONFIG_SOC_DM365)
-	return pll_div(pllbase, PLLC_PREDIV);
-#endif
 	return 1;
 }
 
 static inline unsigned pll_postdiv(volatile void *pllbase)
 {
-#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
-	return pll_div(pllbase, PLLC_POSTDIV);
-#elif defined(CONFIG_SOC_DM6446)
-	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-		return pll_div(pllbase, PLLC_POSTDIV);
-#endif
 	return 1;
 }
 
 static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 {
 	volatile void	*pllbase = (volatile void *) pll_addr;
-#ifdef CONFIG_SOC_DM646X
-	unsigned	base = CONFIG_REFCLK_FREQ / 1000;
-#else
 	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
-#endif
 
 	/* the PLL might be bypassed */
 	if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
 		base /= pll_prediv(pllbase);
-#if defined(CONFIG_SOC_DM365)
-		base *=  2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
-#else
 		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
-#endif
 		base /= pll_postdiv(pllbase);
 	}
 	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
@@ -177,19 +136,9 @@ unsigned int davinci_arm_clk_get()
 }
 #endif
 
-#if defined(CONFIG_SOC_DM365)
-unsigned int davinci_clk_get(unsigned int div)
-{
-	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
-}
-#endif
-
 int set_cpu_clk_info(void)
 {
 	unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
-#if defined(CONFIG_SOC_DM365)
-	pllbase = DAVINCI_PLL_CNTRL1_BASE;
-#endif
 	gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
 
 #ifdef DSP_PLLDIV
@@ -200,9 +149,6 @@ int set_cpu_clk_info(void)
 #endif
 
 	pllbase = DAVINCI_PLL_CNTRL1_BASE;
-#if defined(CONFIG_SOC_DM365)
-	pllbase = DAVINCI_PLL_CNTRL0_BASE;
-#endif
 	gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
 
 	return 0;
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
deleted file mode 100644
index f9550a1..0000000
--- a/arch/arm/mach-davinci/dm355.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * SoC-specific code for tms320dm355 and similar chips
- *
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX3) |= (1 << 20) | (1 << 19);
-}
-#endif
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
deleted file mode 100644
index f6ca527..0000000
--- a/arch/arm/mach-davinci/dm365.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * SoC-specific code for tms320dm365 and similar chips
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-}
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-}
-#endif
diff --git a/arch/arm/mach-davinci/dm365_lowlevel.c b/arch/arm/mach-davinci/dm365_lowlevel.c
deleted file mode 100644
index c8b4498..0000000
--- a/arch/arm/mach-davinci/dm365_lowlevel.c
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- * SoC-specific lowlevel code for tms320dm365 and similar chips
- * Actually used for booting from NAND with nand_spl.
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <nand.h>
-#include <ns16550.h>
-#include <post.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/dm365_lowlevel.h>
-#include <asm/arch/hardware.h>
-
-void dm365_waitloop(unsigned long loopcnt)
-{
-	unsigned long	i;
-
-	for (i = 0; i < loopcnt; i++)
-		asm("   NOP");
-}
-
-int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
-{
-	unsigned int clksrc = 0x0;
-
-	/* Power up the PLL */
-	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
-
-	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
-	setbits_le32(&dv_pll0_regs->pllctl,
-		clksrc << PLLCTL_CLOCK_MODE_SHIFT);
-
-	/*
-	 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
-	 * through MMR
-	 */
-	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
-
-	/* Set PLLEN=0 => PLL BYPASS MODE */
-	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
-
-	dm365_waitloop(150);
-
-	 /* PLLRST=1(reset assert) */
-	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
-
-	dm365_waitloop(300);
-
-	/*Bring PLL out of Reset*/
-	clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
-
-	/* Program the Multiper and Pre-Divider for PLL1 */
-	writel(pllmult, &dv_pll0_regs->pllm);
-	writel(prediv, &dv_pll0_regs->prediv);
-
-	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
-	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
-		PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
-	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
-	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
-		&dv_pll0_regs->secctl);
-	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
-	writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
-	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
-	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
-
-	/* Program the PostDiv for PLL1 */
-	writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
-
-	/* Post divider setting for PLL1 */
-	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
-	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
-	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
-	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
-	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
-	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
-	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
-	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
-	writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
-
-	dm365_waitloop(300);
-
-	/* Set the GOSET bit */
-	writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
-
-	dm365_waitloop(300);
-
-	/* Wait for PLL to LOCK */
-	while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
-		== PLL0_LOCK))
-		;
-
-	/* Enable the PLL Bit of PLLCTL*/
-	setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
-
-	return 0;
-}
-
-int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
-{
-	unsigned int clksrc = 0x0;
-
-	/* Power up the PLL*/
-	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
-
-	/*
-	 * Select the Clock Mode as Onchip Oscilator or External Clock on
-	 * MXI pin
-	 * VDB has input on MXI pin
-	 */
-	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
-	setbits_le32(&dv_pll1_regs->pllctl,
-		clksrc << PLLCTL_CLOCK_MODE_SHIFT);
-
-	/*
-	 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
-	 * through MMR
-	 */
-	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
-
-	/* Set PLLEN=0 => PLL BYPASS MODE */
-	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
-
-	dm365_waitloop(50);
-
-	 /* PLLRST=1(reset assert) */
-	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
-
-	dm365_waitloop(300);
-
-	/* Bring PLL out of Reset */
-	clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
-
-	/* Program the Multiper and Pre-Divider for PLL2 */
-	writel(pllm, &dv_pll1_regs->pllm);
-	writel(prediv, &dv_pll1_regs->prediv);
-
-	writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
-
-	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
-	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
-		PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
-	/* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
-	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
-		&dv_pll1_regs->secctl);
-	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
-	writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
-	/* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
-	writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
-
-	/* Post divider setting for PLL2 */
-	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
-	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
-	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
-	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
-	writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
-
-	/* GoCmd for PostDivider to take effect */
-	writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
-
-	dm365_waitloop(150);
-
-	/* Wait for PLL to LOCK */
-	while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
-		== PLL1_LOCK))
-		;
-
-	dm365_waitloop(4100);
-
-	/* Enable the PLL2 */
-	setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
-
-	/* do this after PLL's have been set up */
-	writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
-		&dv_sys_module_regs->peri_clkctl);
-
-	return 0;
-}
-
-int dm365_ddr_setup(void)
-{
-	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-	clrbits_le32(&dv_sys_module_regs->vtpiocr,
-		VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
-
-	/* Set bit CLRZ (bit 13) */
-	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
-
-	/* Check VTP READY Status */
-	while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
-		;
-
-	/* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
-	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
-
-	/* Set bit LOCK(bit7) */
-	setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
-
-	/*
-	 * Powerdown VTP as it is locked (bit 6)
-	 * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
-	 */
-	setbits_le32(&dv_sys_module_regs->vtpiocr,
-		VPTIO_IOPWRDN | VPTIO_PWRDN);
-
-	/* Wait for calibration to complete */
-	dm365_waitloop(150);
-
-	/* Set the DDR2 to synreset, then enable it again */
-	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
-	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
-	writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-
-	/* Program SDRAM Bank Config Register */
-	writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
-		&dv_ddr2_regs_ctrl->sdbcr);
-	writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
-		&dv_ddr2_regs_ctrl->sdbcr);
-
-	/* Program SDRAM Timing Control Register1 */
-	writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
-	/* Program SDRAM Timing Control Register2 */
-	writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
-
-	writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
-
-	writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
-
-	/* Program SDRAM Refresh Control Register */
-	writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
-
-	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
-	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
-	return 0;
-}
-
-static void dm365_vpss_sync_reset(void)
-{
-	unsigned int PdNum = 0;
-
-	/* VPSS_CLKMD 1:1 */
-	setbits_le32(&dv_sys_module_regs->vpss_clkctl,
-		VPSS_CLK_CTL_VPSS_CLKMD);
-
-	/* LPSC SyncReset DDR Clock Enable */
-	writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
-		~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
-		&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
-
-	writel((1 << PdNum), &dv_psc_regs->ptcmd);
-
-	while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
-		;
-	while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
-		PSC_MD_STATE_MSK) == PSC_SYNCRESET))
-		;
-}
-
-static void dm365_por_reset(void)
-{
-	struct davinci_timer *wdog =
-		(struct davinci_timer *)DAVINCI_WDOG_BASE;
-
-	if (readl(&dv_pll0_regs->rstype) &
-		(PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
-		dm365_vpss_sync_reset();
-
-		writel(DV_TMPBUF_VAL, TMPBUF);
-		setbits_le32(TMPSTATUS, FLAG_PORRST);
-		writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
-		writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
-
-		while (1);
-	}
-}
-
-static void dm365_wdt_reset(void)
-{
-	struct davinci_timer *wdog =
-		(struct davinci_timer *)DAVINCI_WDOG_BASE;
-
-	if (readl(TMPBUF) != DV_TMPBUF_VAL) {
-		writel(DV_TMPBUF_VAL, TMPBUF);
-		setbits_le32(TMPSTATUS, FLAG_PORRST);
-		setbits_le32(TMPSTATUS, FLAG_FLGOFF);
-
-		dm365_waitloop(100);
-
-		dm365_vpss_sync_reset();
-
-		writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
-		writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
-
-		while (1);
-	}
-}
-
-static void dm365_wdt_flag_on(void)
-{
-	/* VPSS_CLKMD 1:2 */
-	clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
-		VPSS_CLK_CTL_VPSS_CLKMD);
-	writel(0, TMPBUF);
-	setbits_le32(TMPSTATUS, FLAG_FLGON);
-}
-
-void dm365_psc_init(void)
-{
-	unsigned char i = 0;
-	unsigned char lpsc_start;
-	unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
-	unsigned int  PdNum = 0;
-
-	lpscmin = 0;
-	lpscmax = 2;
-
-	for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
-		if (lpscgroup == 0) {
-			/* Enabling LPSC 3 to 28 SCR first */
-			lpsc_start = DAVINCI_LPSC_VPSSMSTR;
-			lpsc_end   = DAVINCI_LPSC_TIMER1;
-		} else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
-			lpsc_start = DAVINCI_LPSC_CFG5;
-			lpsc_end   = DAVINCI_LPSC_VPSSMASTER;
-		} else {
-			lpsc_start = DAVINCI_LPSC_MJCP;
-			lpsc_end   = DAVINCI_LPSC_HDVICP;
-		}
-
-		/* NEXT=0x3, Enable LPSC's */
-		for (i = lpsc_start; i <= lpsc_end; i++)
-			setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
-
-		/*
-		 * Program goctl to start transition sequence for LPSCs
-		 * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
-		 * Domain 0 Modules
-		 */
-		writel((1 << PdNum), &dv_psc_regs->ptcmd);
-
-		/*
-		 * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
-		 */
-		while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
-			== 0))
-			;
-
-		/* Wait for MODSTAT = ENABLE from LPSC's */
-		for (i = lpsc_start; i <= lpsc_end; i++)
-			while (!((readl(&dv_psc_regs->mdstat[i]) &
-				PSC_MD_STATE_MSK) == PSC_ENABLE))
-				;
-	}
-}
-
-static void dm365_emif_init(void)
-{
-	writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
-	writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
-
-	setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
-
-	writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
-
-	return;
-}
-
-void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
-	unsigned long value)
-{
-	clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
-	setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
-}
-
-__attribute__((weak))
-void board_gpio_init(void)
-{
-	return;
-}
-
-#if defined(CONFIG_POST)
-int post_log(char *format, ...)
-{
-	return 0;
-}
-#endif
-
-void dm36x_lowlevel_init(ulong bootflag)
-{
-	struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
-		(struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
-		DAVINCI_UART_CTRL_BASE);
-
-	/* Mask all interrupts */
-	writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
-	writel(0x0, &dv_aintc_regs->eabase);
-	writel(0x0, &dv_aintc_regs->eint0);
-	writel(0x0, &dv_aintc_regs->eint1);
-
-	/* Clear all interrupts */
-	writel(0xffffffff, &dv_aintc_regs->fiq0);
-	writel(0xffffffff, &dv_aintc_regs->fiq1);
-	writel(0xffffffff, &dv_aintc_regs->irq0);
-	writel(0xffffffff, &dv_aintc_regs->irq1);
-
-	dm365_por_reset();
-	dm365_wdt_reset();
-
-	/* System PSC setup - enable all */
-	dm365_psc_init();
-
-	/* Setup Pinmux */
-	dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
-	dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
-	dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
-	dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
-	dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
-
-	/* PLL setup */
-	dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
-		CONFIG_SYS_DM36x_PLL1_PREDIV);
-	dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
-		CONFIG_SYS_DM36x_PLL2_PREDIV);
-
-	/* GPIO setup */
-	board_gpio_init();
-
-	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
-			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
-	/*
-	 * Fix Power and Emulation Management Register
-	 * see sprufh2.pdf page 38 Table 22
-	 */
-	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
-		DAVINCI_UART_PWREMU_MGMT_UTRST),
-	       &davinci_uart_ctrl_regs->pwremu_mgmt);
-
-	puts("ddr init\n");
-	dm365_ddr_setup();
-
-	puts("emif init\n");
-	dm365_emif_init();
-
-	dm365_wdt_flag_on();
-
-#if defined(CONFIG_POST)
-	/*
-	 * Do memory tests, calls arch_memory_failure_handle()
-	 * if error detected.
-	 */
-	memory_post_test(0);
-#endif
-}
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
deleted file mode 100644
index c58e271..0000000
--- a/arch/arm/mach-davinci/dm644x.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * SoC-specific code for tms320dm644x chips
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-#define PINMUX0_EMACEN (1 << 31)
-#define PINMUX0_AECS5  (1 << 11)
-#define PINMUX0_AECS4  (1 << 10)
-
-#define PINMUX1_I2C    (1 <<  7)
-#define PINMUX1_UART1  (1 <<  1)
-#define PINMUX1_UART0  (1 <<  0)
-
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x00006001;
-
-	/* Enable UART0 MUX lines */
-	REG(PINMUX1) |= PINMUX1_UART0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-	lpsc_on(DAVINCI_LPSC_EMAC);
-	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
-	lpsc_on(DAVINCI_LPSC_MDIO);
-
-	/* Enable GIO3.3V cells used for EMAC */
-	REG(VDD3P3V_PWDN) = 0;
-
-	/* Enable EMAC. */
-	REG(PINMUX0) |= PINMUX0_EMACEN;
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX1) |= PINMUX1_I2C;
-}
-#endif
-
-void davinci_errata_workarounds(void)
-{
-	/*
-	 * Workaround for TMS320DM6446 errata 1.3.22:
-	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
-	 *   Revision(s) Affected: 1.3 and earlier
-	 */
-	REG(PSC_SILVER_BULLET) = 0;
-
-	/*
-	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
-	 * as suggested in TMS320DM6446 errata 2.1.2:
-	 *
-	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
-	 * low priority modules can occupy the bus and prevent high priority
-	 * modules like the VPSS from getting the required DDR2 throughput.
-	 * A hex value of 0x20 should provide a good ARM (cache enabled)
-	 * performance and still allow good utilization by the VPSS or other
-	 * modules.
-	 */
-	REG(VBPR) = 0x20;
-}
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
deleted file mode 100644
index cfea830..0000000
--- a/arch/arm/mach-davinci/dm646x.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * SoC-specific code for TMS320DM646x chips
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_DM646X_LPSC_UART0);
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-	lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_DM646X_LPSC_I2C);
-}
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/aintc_defs.h b/arch/arm/mach-davinci/include/mach/aintc_defs.h
deleted file mode 100644
index 5063e39..0000000
--- a/arch/arm/mach-davinci/include/mach/aintc_defs.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _DV_AINTC_DEFS_H_
-#define _DV_AINTC_DEFS_H_
-
-struct dv_aintc_regs {
-	unsigned int	fiq0;		/* 0x00 */
-	unsigned int	fiq1;		/* 0x04 */
-	unsigned int	irq0;		/* 0x08 */
-	unsigned int	irq1;		/* 0x0c */
-	unsigned int	fiqentry;	/* 0x10 */
-	unsigned int	irqentry;	/* 0x14 */
-	unsigned int	eint0;		/* 0x18 */
-	unsigned int	eint1;		/* 0x1c */
-	unsigned int	intctl;		/* 0x20 */
-	unsigned int	eabase;		/* 0x24 */
-	unsigned char	rsvd0[8];	/* 0x28 */
-	unsigned int	intpri0;	/* 0x30 */
-	unsigned int	intpri1;	/* 0x34 */
-	unsigned int	intpri2;	/* 0x38 */
-	unsigned int	intpri3;	/* 0x3c */
-	unsigned int	intpri4;	/* 0x40 */
-	unsigned int	intpri5;	/* 0x44 */
-	unsigned int	intpri6;	/* 0x48 */
-	unsigned int	intpri7;	/* 0x4c */
-};
-
-#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
-
-#define DV_AINTC_INTCTL_IDMODE	(1 << 2)
-
-#endif /* _DV_AINTC_DEFS_H_ */
diff --git a/arch/arm/mach-davinci/include/mach/emac_defs.h b/arch/arm/mach-davinci/include/mach/emac_defs.h
index c3f046e..17a9277 100644
--- a/arch/arm/mach-davinci/include/mach/emac_defs.h
+++ b/arch/arm/mach-davinci/include/mach/emac_defs.h
@@ -24,13 +24,7 @@
 
 #include <asm/arch/hardware.h>
 
-#ifdef CONFIG_SOC_DM365
-#define EMAC_BASE_ADDR			(0x01d07000)
-#define EMAC_WRAPPER_BASE_ADDR		(0x01d0a000)
-#define EMAC_WRAPPER_RAM_ADDR		(0x01d08000)
-#define EMAC_MDIO_BASE_ADDR		(0x01d0b000)
-#define DAVINCI_EMAC_VERSION2
-#elif defined(CONFIG_SOC_DA8XX)
+#if defined(CONFIG_SOC_DA8XX)
 #define EMAC_BASE_ADDR			DAVINCI_EMAC_CNTRL_REGS_BASE
 #define EMAC_WRAPPER_BASE_ADDR		DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
 #define EMAC_WRAPPER_RAM_ADDR		DAVINCI_EMAC_WRAPPER_RAM_BASE
@@ -43,22 +37,7 @@
 #define EMAC_MDIO_BASE_ADDR		(0x01c84000)
 #endif
 
-#ifdef CONFIG_SOC_DM646X
-#define DAVINCI_EMAC_VERSION2
-#define DAVINCI_EMAC_GIG_ENABLE
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ		76500000
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		2500000		/* 2.5 MHz */
-#elif defined(CONFIG_SOC_DM365)
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ		121500000
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ		2200000		/* 2.2 MHz */
-#elif defined(CONFIG_SOC_DA8XX)
+#if defined(CONFIG_SOC_DA8XX)
 /* MDIO module input frequency */
 #define EMAC_MDIO_BUS_FREQ		clk_get(DAVINCI_MDIO_CLKID)
 /* MDIO clock output frequency */
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index 7da0060..d48706a 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -51,10 +51,7 @@ struct davinci_gpio_bank {
 
 #define gpio_status()		gpio_info()
 #define GPIO_NAME_SIZE		20
-#if defined(CONFIG_SOC_DM644X)
-/* GPIO0 to GPIO53, omit the V3.3 volts one */
-#define MAX_NUM_GPIOS		70
-#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
+#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
 #define MAX_NUM_GPIOS		128
 #else
 #define MAX_NUM_GPIOS		144
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index a4eb0bd..80927bd 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -56,54 +56,12 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_SPI_BASE			(0x01c66800)
 #define DAVINCI_GPIO_BASE			(0x01c67000)
 #define DAVINCI_VPSS_REGS_BASE			(0x01c70000)
-#if !defined(CONFIG_SOC_DM646X)
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x02000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
-#endif
 #define DAVINCI_DDR_BASE			(0x80000000)
 
-#ifdef CONFIG_SOC_DM644X
-#define DAVINCI_UART2_BASE			0x01c20800
-#define DAVINCI_UHPI_BASE			0x01c67800
-#define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01c80000
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01c81000
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01c82000
-#define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01c84000
-#define DAVINCI_IMCOP_BASE			0x01cc0000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e00000
-#define DAVINCI_VLYNQ_BASE			0x01e01000
-#define DAVINCI_ASP_BASE			0x01e02000
-#define DAVINCI_MMC_SD_BASE			0x01e10000
-#define DAVINCI_MS_BASE				0x01e20000
-#define DAVINCI_VLYNQ_REMOTE_BASE		0x0c000000
-
-#elif defined(CONFIG_SOC_DM355)
-#define DAVINCI_MMC_SD1_BASE			0x01e00000
-#define DAVINCI_ASP0_BASE			0x01e02000
-#define DAVINCI_ASP1_BASE			0x01e04000
-#define DAVINCI_UART2_BASE			0x01e06000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e10000
-#define DAVINCI_MMC_SD0_BASE			0x01e11000
-
-#elif defined(CONFIG_SOC_DM365)
-#define DAVINCI_MMC_SD1_BASE			0x01d00000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01d10000
-#define DAVINCI_MMC_SD0_BASE			0x01d11000
-#define DAVINCI_DDR_EMIF_CTRL_BASE		0x20000000
-#define DAVINCI_SPI0_BASE			0x01c66000
-#define DAVINCI_SPI1_BASE			0x01c66800
-
-#elif defined(CONFIG_SOC_DM646X)
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x20008000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	0x42000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	0x44000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	0x46000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
-
-#endif
-
 #else /* CONFIG_SOC_DA8XX */
 
 #define DAVINCI_UART0_BASE			0x01c42000
@@ -594,23 +552,4 @@ static inline enum davinci_clk_ids get_async3_src(void)
 
 #endif /* CONFIG_SOC_DA8XX */
 
-#if defined(CONFIG_SOC_DM365)
-#include <asm/arch/aintc_defs.h>
-#include <asm/arch/ddr2_defs.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pll_defs.h>
-#include <asm/arch/psc_defs.h>
-#include <asm/arch/syscfg_defs.h>
-#include <asm/arch/timer_defs.h>
-
-#define TMPBUF			0x00017ff8
-#define TMPSTATUS		0x00017ff0
-#define DV_TMPBUF_VAL		0x591b3ed7
-#define FLAG_PORRST		0x00000001
-#define FLAG_WDTRST		0x00000002
-#define FLAG_FLGON		0x00000004
-#define FLAG_FLGOFF		0x00000010
-
-#endif
-
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc_defs.h b/arch/arm/mach-davinci/include/mach/psc_defs.h
deleted file mode 100644
index bcb5580..0000000
--- a/arch/arm/mach-davinci/include/mach/psc_defs.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _DV_PSC_DEFS_H_
-#define _DV_PSC_DEFS_H_
-
-/*
- * Power/Sleep Ctrl Register structure
- * See sprufb3.pdf, Chapter 7
- */
-struct dv_psc_regs {
-	unsigned int	pid;		/* 0x000 */
-	unsigned char	rsvd0[16];	/* 0x004 */
-	unsigned char	rsvd1[4];	/* 0x014 */
-	unsigned int	inteval;	/* 0x018 */
-	unsigned char	rsvd2[36];	/* 0x01C */
-	unsigned int	merrpr0;	/* 0x040 */
-	unsigned int	merrpr1;	/* 0x044 */
-	unsigned char	rsvd3[8];	/* 0x048 */
-	unsigned int	merrcr0;	/* 0x050 */
-	unsigned int	merrcr1;	/* 0x054 */
-	unsigned char	rsvd4[8];	/* 0x058 */
-	unsigned int	perrpr;		/* 0x060 */
-	unsigned char	rsvd5[4];	/* 0x064 */
-	unsigned int	perrcr;		/* 0x068 */
-	unsigned char	rsvd6[4];	/* 0x06C */
-	unsigned int	epcpr;		/* 0x070 */
-	unsigned char	rsvd7[4];	/* 0x074 */
-	unsigned int	epccr;		/* 0x078 */
-	unsigned char	rsvd8[144];	/* 0x07C */
-	unsigned char	rsvd9[20];	/* 0x10C */
-	unsigned int	ptcmd;		/* 0x120 */
-	unsigned char	rsvd10[4];	/* 0x124 */
-	unsigned int	ptstat;		/* 0x128 */
-	unsigned char	rsvd11[212];	/* 0x12C */
-	unsigned int	pdstat0;	/* 0x200 */
-	unsigned int	pdstat1;	/* 0x204 */
-	unsigned char	rsvd12[248];	/* 0x208 */
-	unsigned int	pdctl0;		/* 0x300 */
-	unsigned int	pdctl1;		/* 0x304 */
-	unsigned char	rsvd13[536];	/* 0x308 */
-	unsigned int	mckout0;	/* 0x520 */
-	unsigned int	mckout1;	/* 0x524 */
-	unsigned char	rsvd14[728];	/* 0x528 */
-	unsigned int	mdstat[52];	/* 0x800 */
-	unsigned char	rsvd15[304];	/* 0x8D0 */
-	unsigned int	mdctl[52];	/* 0xA00 */
-};
-
-/* PSC constants */
-#define EMURSTIE_MASK	(0x00000200)
-
-#define PD0		(0)
-
-#define PSC_ENABLE		(0x3)
-#define PSC_DISABLE		(0x2)
-#define PSC_SYNCRESET		(0x1)
-#define PSC_SWRSTDISABLE	(0x0)
-
-#define PSC_GOSTAT		(1 << 0)
-#define PSC_MD_STATE_MSK	(0x1f)
-
-#define PSC_CMD_GO		(1 << 0)
-
-#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
-
-#endif /* _DV_PSC_DEFS_H_ */
diff --git a/arch/arm/mach-davinci/include/mach/syscfg_defs.h b/arch/arm/mach-davinci/include/mach/syscfg_defs.h
deleted file mode 100644
index 812088f..0000000
--- a/arch/arm/mach-davinci/include/mach/syscfg_defs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _DV_SYSCFG_DEFS_H_
-#define _DV_SYSCFG_DEFS_H_
-
-#ifndef CONFIG_SOC_DA8XX
-/* System Control Module register structure for DM365 */
-struct dv_sys_module_regs {
-	unsigned int	pinmux[5];	/* 0x00 */
-	unsigned int	bootcfg;	/* 0x14 */
-	unsigned int	arm_intmux;	/* 0x18 */
-	unsigned int	edma_evtmux;	/* 0x1C */
-	unsigned int	ddr_slew;	/* 0x20 */
-	unsigned int	clkout;		/* 0x24 */
-	unsigned int	device_id;	/* 0x28 */
-	unsigned int	vdac_config;	/* 0x2C */
-	unsigned int	timer64_ctl;	/* 0x30 */
-	unsigned int	usbbphy_ctl;	/* 0x34 */
-	unsigned int	misc;		/* 0x38 */
-	unsigned int	mstpri[2];	/* 0x3C */
-	unsigned int	vpss_clkctl;	/* 0x44 */
-	unsigned int	peri_clkctl;	/* 0x48 */
-	unsigned int	deepsleep;	/* 0x4C */
-	unsigned int	dft_enable;	/* 0x50 */
-	unsigned int	debounce[8];	/* 0x54 */
-	unsigned int	vtpiocr;	/* 0x74 */
-	unsigned int	pupdctl0;	/* 0x78 */
-	unsigned int	pupdctl1;	/* 0x7C */
-	unsigned int	hdimcopbt;	/* 0x80 */
-	unsigned int	pll0_config;	/* 0x84 */
-	unsigned int	pll1_config;	/* 0x88 */
-};
-
-#define VPTIO_RDY	(1 << 15)
-#define VPTIO_IOPWRDN	(1 << 14)
-#define VPTIO_CLRZ	(1 << 13)
-#define VPTIO_LOCK	(1 << 7)
-#define VPTIO_PWRDN	(1 << 6)
-
-#define VPSS_CLK_CTL_VPSS_CLKMD	(1 << 7)
-
-#define dv_sys_module_regs \
-	((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
-
-#endif /* !CONFIG_SOC_DA8XX */
-#endif /* _DV_SYSCFG_DEFS_H_ */
diff --git a/arch/arm/mach-davinci/lowlevel_init.S b/arch/arm/mach-davinci/lowlevel_init.S
index e916234..1183e11 100644
--- a/arch/arm/mach-davinci/lowlevel_init.S
+++ b/arch/arm/mach-davinci/lowlevel_init.S
@@ -24,670 +24,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <config.h>
-
-#define MDSTAT_STATE	0x3f
-
 .globl	lowlevel_init
 lowlevel_init:
-#ifdef CONFIG_SOC_DM644X
-
-	/*-------------------------------------------------------*
-	 * Mask all IRQs by setting all bits in the EINT default *
-	 *-------------------------------------------------------*/
-	mov	r1, $0
-	ldr	r0, =EINT_ENABLE0
-	str	r1, [r0]
-	ldr	r0, =EINT_ENABLE1
-	str	r1, [r0]
-
-	/*------------------------------------------------------*
-	 * Put the GEM in reset					*
-	 *------------------------------------------------------*/
-
-	/* Put the GEM in reset */
-	ldr	r8, PSC_GEM_FLAG_CLEAR
-	ldr	r6, MDCTL_GEM
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x02
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStopGem:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x02
-	bne	checkStatClkStopGem
-
-	/* Check for GEM Reset Completion */
-checkGemStatClkStop:
-	ldr	r6, MDSTAT_GEM
-	ldr	r7, [r6]
-	ands	r7, r7, $0x100
-	bne	checkGemStatClkStop
-
-	/* Do this for enabling a WDT initiated reset this is a workaround
-	   for a chip bug.  Not required under normal situations */
-	ldr	r6, P1394
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*------------------------------------------------------*
-	 * Enable L1 & L2 Memories in Fast mode                 *
-	 *------------------------------------------------------*/
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0x01
-	str	r10, [r6]
-
-	ldr	r6, MMARG_BRF0
-	ldr	r10, MMARG_BRF0_VAL
-	str	r10, [r6]
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*------------------------------------------------------*
-	 * DDR2 PLL Initialization				*
-	 *------------------------------------------------------*/
-
-	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
-	mov	r10, $0
-	ldr	r6, PLL2_CTL
-	ldr	r7, PLL_CLKSRC_MASK
-	ldr	r8, [r6]
-	and	r8, r8, r7
-	mov	r9, r10, lsl $8
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Select the PLLEN source */
-	ldr	r7, PLL_ENSRC_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Bypass the PLL */
-	ldr	r7, PLL_BYPASS_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-	mov	r10, $0x20
-WaitPPL2Loop:
-	subs	r10, r10, $1
-	bne	WaitPPL2Loop
-
-	/* Reset the PLL */
-	ldr	r7, PLL_RESET_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Power up the PLL */
-	ldr	r7, PLL_PWRUP_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Enable the PLL from Disable Mode */
-	ldr	r7, PLL_DISABLE_ENABLE_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Program the PLL Multiplier */
-	ldr	r6, PLL2_PLLM
-	mov	r2, $0x17	/* 162 MHz */
-	str	r2, [r6]
-
-	/* Program the PLL2 Divisor Value */
-	ldr	r6, PLL2_DIV2
-	mov	r3, $0x01
-	str	r3, [r6]
-
-	/* Program the PLL2 Divisor Value */
-	ldr	r6, PLL2_DIV1
-	mov	r4, $0x0b	/* 54 MHz */
-	str	r4, [r6]
-
-	/* PLL2 DIV2 MMR */
-	ldr	r8, PLL2_DIV_MASK
-	ldr	r6, PLL2_DIV2
-	ldr	r9, [r6]
-	and	r8, r8, r9
-	mov	r9, $0x01
-	mov	r9, r9, lsl $15
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Program the GOSET bit to take new divider values */
-	ldr	r6, PLL2_PLLCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Wait for Done */
-	ldr	r6, PLL2_PLLSTAT
-doneLoop_0:
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	doneLoop_0
-
-	/* PLL2 DIV1 MMR */
-	ldr	r8, PLL2_DIV_MASK
-	ldr	r6, PLL2_DIV1
-	ldr	r9, [r6]
-	and	r8, r8, r9
-	mov	r9, $0x01
-	mov	r9, r9, lsl $15
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Program the GOSET bit to take new divider values */
-	ldr	r6, PLL2_PLLCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Wait for Done */
-	ldr	r6, PLL2_PLLSTAT
-doneLoop:
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	doneLoop
-
-	/* Wait for PLL to Reset Properly */
-	mov	r10, $0x218
-ResetPPL2Loop:
-	subs	r10, r10, $1
-	bne	ResetPPL2Loop
-
-	/* Bring PLL out of Reset */
-	ldr	r6, PLL2_CTL
-	ldr	r8, [r6]
-	orr	r8, r8, $0x08
-	str	r8, [r6]
-
-	/* Wait for PLL to Lock */
-	ldr	r10, PLL_LOCK_COUNT
-PLL2Lock:
-	subs	r10, r10, $1
-	bne	PLL2Lock
-
-	/* Enable the PLL */
-	ldr	r6, PLL2_CTL
-	ldr	r8, [r6]
-	orr	r8, r8, $0x01
-	str	r8, [r6]
-
-	/*------------------------------------------------------*
-	 * Issue Soft Reset to DDR Module			*
-	 *------------------------------------------------------*/
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x03
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $MDSTAT_STATE
-	cmp	r7, $0x03
-	bne	checkDDRStatClkStop
-
-	/*------------------------------------------------------*
-	 * Program DDR2 MMRs for 162MHz Setting			*
-	 *------------------------------------------------------*/
-
-	/* Program PHY Control Register */
-	ldr	r6, DDRCTL
-	ldr	r7, DDRCTL_VAL
-	str	r7, [r6]
-
-	/* Program SDRAM Bank Config Register */
-	ldr	r6, SDCFG
-	ldr	r7, SDCFG_VAL
-	str	r7, [r6]
-
-	/* Program SDRAM TIM-0 Config Register */
-	ldr	r6, SDTIM0
-	ldr	r7, SDTIM0_VAL_162MHz
-	str	r7, [r6]
-
-	/* Program SDRAM TIM-1 Config Register */
-	ldr	r6, SDTIM1
-	ldr	r7, SDTIM1_VAL_162MHz
-	str	r7, [r6]
-
-	/* Program the SDRAM Bank Config Control Register */
-	ldr	r10, MASK_VAL
-	ldr	r8, SDCFG
-	ldr	r9, SDCFG_VAL
-	and	r9, r9, r10
-	str	r9, [r8]
-
-	/* Program SDRAM SDREF Config Register */
-	ldr	r6, SDREF
-	ldr	r7, SDREF_VAL
-	str	r7, [r6]
-
-	/*------------------------------------------------------*
-	 * Issue Soft Reset to DDR Module			*
-	 *------------------------------------------------------*/
-
-	/* Issue a Dummy DDR2 read/write */
-	ldr	r8, DDR2_START_ADDR
-	ldr	r7, DUMMY_VAL
-	str	r7, [r8]
-	ldr	r7, [r8]
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop2
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $MDSTAT_STATE
-	cmp	r7, $0x01
-	bne	checkDDRStatClkStop2
-
-	/*------------------------------------------------------*
-	 * Turn DDR2 Controller Clocks On			*
-	 *------------------------------------------------------*/
-
-	/* Enable the DDR2 LPSC Module */
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	orr	r7, r7, $0x03
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkEn2:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkEn2
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkEn2:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $MDSTAT_STATE
-	cmp	r7, $0x03
-	bne	checkDDRStatClkEn2
-
-	/*  DDR Writes and Reads */
-	ldr	r6, CFGTEST
-	mov	r3, $0x01
-	str	r3, [r6]
-
-	/*------------------------------------------------------*
-	 * System PLL Initialization				*
-	 *------------------------------------------------------*/
-
-	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
-	mov	r2, $0
-	ldr	r6, PLL1_CTL
-	ldr	r7, PLL_CLKSRC_MASK
-	ldr	r8, [r6]
-	and	r8, r8, r7
-	mov	r9, r2, lsl $8
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Select the PLLEN source */
-	ldr	r7, PLL_ENSRC_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Bypass the PLL */
-	ldr	r7, PLL_BYPASS_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-	mov	r10, $0x20
-
-WaitLoop:
-	subs	r10, r10, $1
-	bne	WaitLoop
-
-	/* Reset the PLL */
-	ldr	r7, PLL_RESET_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Disable the PLL */
-	orr	r8, r8, $0x10
-	str	r8, [r6]
-
-	/* Power up the PLL */
-	ldr	r7, PLL_PWRUP_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Enable the PLL from Disable Mode */
-	ldr	r7, PLL_DISABLE_ENABLE_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Program the PLL Multiplier */
-	ldr	r6, PLL1_PLLM
-	mov	r3, $0x15	/* For 594MHz */
-	str	r3, [r6]
-
-	/* Wait for PLL to Reset Properly */
-	mov	r10, $0xff
-
-ResetLoop:
-	subs	r10, r10, $1
-	bne	ResetLoop
-
-	/* Bring PLL out of Reset */
-	ldr	r6, PLL1_CTL
-	orr	r8, r8, $0x08
-	str	r8, [r6]
-
-	/* Wait for PLL to Lock */
-	ldr	r10, PLL_LOCK_COUNT
-
-PLL1Lock:
-	subs	r10, r10, $1
-	bne	PLL1Lock
-
-	/* Enable the PLL */
-	orr	r8, r8, $0x01
-	str	r8, [r6]
-
-	nop
-	nop
-	nop
-	nop
-
-	/*------------------------------------------------------*
-	 * AEMIF configuration for NOR Flash (double check)     *
-	 *------------------------------------------------------*/
-	ldr	r0, _PINMUX0
-	ldr	r1, _DEV_SETTING
-	str	r1, [r0]
-
-	ldr	r0, WAITCFG
-	ldr	r1, WAITCFG_VAL
-	ldr	r2, [r0]
-	orr	r2, r2, r1
-	str	r2, [r0]
-
-	ldr	r0, ACFG3
-	ldr	r1, ACFG3_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	ldr	r0, ACFG4
-	ldr	r1, ACFG4_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	ldr	r0, ACFG5
-	ldr	r1, ACFG5_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	/*--------------------------------------*
-	 * VTP manual Calibration               *
-	 *--------------------------------------*/
-	ldr	r0, VTPIOCR
-	ldr	r1, VTP_MMR0
-	str	r1, [r0]
-
-	ldr	r0, VTPIOCR
-	ldr	r1, VTP_MMR1
-	str	r1, [r0]
-
-	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
-	ldr	r10, VTP_LOCK_COUNT
-VTPLock:
-	subs	r10, r10, $1
-	bne	VTPLock
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0x01
-	str	r10, [r6]
-
-	ldr	r6, DDRVTPR
-	ldr	r7, [r6]
-	mov	r8, r7, LSL #32-10
-	mov	r8, r8, LSR #32-10        /* grab low 10 bits  */
-	ldr	r7, VTP_RECAL
-	orr	r8, r7, r8
-	ldr	r7, VTP_EN
-	orr	r8, r7, r8
-	str	r8, [r0]
-
-
-	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
-	ldr	r10, VTP_LOCK_COUNT
-VTP1Lock:
-	subs	r10, r10, $1
-	bne	VTP1Lock
-
-	ldr	r1, [r0]
-	ldr	r2, VTP_MASK
-	and	r2, r1, r2
-	str	r2, [r0]
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*
-	 * Call board-specific lowlevel init.
-	 * That MUST be present and THAT returns
-	 * back to arch calling code with "mov pc, lr."
-	 */
-	b	dv_board_init
-
-.ltorg
-
-_PINMUX0:
-	.word	0x01c40000		/* Device Configuration Registers */
-_PINMUX1:
-	.word	0x01c40004		/* Device Configuration Registers */
-
-_DEV_SETTING:
-	.word	0x00000c1f
-
-WAITCFG:
-	.word	0x01e00004
-WAITCFG_VAL:
-	.word	0
-ACFG3:
-	.word	0x01e00014
-ACFG3_VAL:
-	.word	0x3ffffffd
-ACFG4:
-	.word	0x01e00018
-ACFG4_VAL:
-	.word	0x3ffffffd
-ACFG5:
-	.word	0x01e0001c
-ACFG5_VAL:
-	.word	0x3ffffffd
-
-MDCTL_DDR2:
-	.word	0x01c41a34
-MDSTAT_DDR2:
-	.word	0x01c41834
-
-PTCMD:
-	.word	0x01c41120
-PTSTAT:
-	.word	0x01c41128
-
-EINT_ENABLE0:
-	.word	0x01c48018
-EINT_ENABLE1:
-	.word	0x01c4801c
-
-PSC_FLAG_CLEAR:
-	.word	0xffffffe0
-PSC_GEM_FLAG_CLEAR:
-	.word	0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-DDRCTL:
-	.word	0x200000e4
-DDRCTL_VAL:
-	.word	0x50006405
-SDREF:
-	.word	0x2000000c
-SDREF_VAL:
-	.word	0x000005c3
-SDCFG:
-	.word	0x20000008
-SDCFG_VAL:
-#ifdef	DDR_4BANKS
-	.word	0x00178622
-#elif defined DDR_8BANKS
-	.word	0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
-SDTIM0:
-	.word	0x20000010
-SDTIM0_VAL_162MHz:
-	.word	0x28923211
-SDTIM1:
-	.word	0x20000014
-SDTIM1_VAL_162MHz:
-	.word	0x0016c722
-VTPIOCR:
-	.word	0x200000f0	/* VTP IO Control register */
-DDRVTPR:
-	.word	0x01c42030	/* DDR VPTR MMR */
-VTP_MMR0:
-	.word	0x201f
-VTP_MMR1:
-	.word	0xa01f
-DFT_ENABLE:
-	.word	0x01c4004c
-VTP_LOCK_COUNT:
-	.word	0x5b0
-VTP_MASK:
-	.word	0xffffdfff
-VTP_RECAL:
-	.word	0x08000
-VTP_EN:
-	.word	0x02000
-CFGTEST:
-	.word	0x80010000
-MASK_VAL:
-	.word	0x00000fff
-
-/* GEM Power Up & LPSC Control Register */
-MDCTL_GEM:
-	.word	0x01c41a9c
-MDSTAT_GEM:
-	.word	0x01c4189c
-
-/* For WDT reset chip bug */
-P1394:
-	.word	0x01c41a20
-
-PLL_CLKSRC_MASK:
-	.word	0xfffffeff	/* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
-	.word	0xffffffdf	/* Select the PLLEN source */
-PLL_BYPASS_MASK:
-	.word	0xfffffffe	/* Put the PLL in BYPASS */
-PLL_RESET_MASK:
-	.word	0xfffffff7	/* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
-	.word	0xfffffffd	/* PLL Power up Mask Bit  */
-PLL_DISABLE_ENABLE_MASK:
-	.word	0xffffffef	/* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
-	.word	0x2000
-
-/* PLL1-SYSTEM PLL MMRs */
-PLL1_CTL:
-	.word	0x01c40900
-PLL1_PLLM:
-	.word	0x01c40910
-
-/* PLL2-SYSTEM PLL MMRs */
-PLL2_CTL:
-	.word	0x01c40d00
-PLL2_PLLM:
-	.word	0x01c40d10
-PLL2_DIV1:
-	.word	0x01c40d18
-PLL2_DIV2:
-	.word	0x01c40d1c
-PLL2_PLLCMD:
-	.word	0x01c40d38
-PLL2_PLLSTAT:
-	.word	0x01c40d3c
-PLL2_DIV_MASK:
-	.word	0xffff7fff
-
-MMARG_BRF0:
-	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
-MMARG_BRF0_VAL:
-	.word	0x00444400
-
-DDR2_START_ADDR:
-	.word	0x80000000
-DUMMY_VAL:
-	.word	0xa55aa55a
-#else /* CONFIG_SOC_DM644X */
 	mov pc, lr
-#endif
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 8d99e2e..6d6e6a9 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -73,28 +73,6 @@ static void lpsc_transition(unsigned int id, unsigned int state)
 
 	writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
 
-	switch (id) {
-#ifdef CONFIG_SOC_DM644X
-	/* Special treatment for some modules as for sprue14 p.7.4.2 */
-	case DAVINCI_LPSC_VPSSSLV:
-	case DAVINCI_LPSC_EMAC:
-	case DAVINCI_LPSC_EMAC_WRAPPER:
-	case DAVINCI_LPSC_MDIO:
-	case DAVINCI_LPSC_USB:
-	case DAVINCI_LPSC_ATA:
-	case DAVINCI_LPSC_VLYNQ:
-	case DAVINCI_LPSC_UHPI:
-	case DAVINCI_LPSC_DDR_EMIF:
-	case DAVINCI_LPSC_AEMIF:
-	case DAVINCI_LPSC_MMC_SD:
-	case DAVINCI_LPSC_MEMSTICK:
-	case DAVINCI_LPSC_McBSP:
-	case DAVINCI_LPSC_GPIO:
-		writel(readl(mdctl) | 0x200, mdctl);
-		break;
-#endif
-	}
-
 	writel(0x01, ptcmd);
 
 	while (readl(ptstat) & 0x01)
@@ -117,44 +95,3 @@ void lpsc_disable(unsigned int id)
 {
 	lpsc_transition(id, 0x0);
 }
-
-/* Not all DaVinci chips have a DSP power domain. */
-#ifdef CONFIG_SOC_DM644X
-
-/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-void dsp_on(void)
-{
-	int i;
-
-	if (REG(PSC_PDSTAT1) & 0x1f)
-		return;			/* Already on */
-
-	REG(PSC_GBLCTL) |= 0x01;
-	REG(PSC_PDCTL1) |= 0x01;
-	REG(PSC_PDCTL1) &= ~0x100;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
-	REG(PSC_PTCMD) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (REG(PSC_EPCPR) & 0x02)
-			break;
-	}
-
-	REG(PSC_CHP_SHRTSW) = 0x01;
-	REG(PSC_PDCTL1) |= 0x100;
-	REG(PSC_EPCCR) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (!(REG(PSC_PTSTAT) & 0x02))
-			break;
-	}
-
-	REG(PSC_GBLCTL) &= ~0x1f;
-}
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-#endif /* have a DSP */
diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c
index 49349da..0fe1916 100644
--- a/arch/arm/mach-davinci/spl.c
+++ b/arch/arm/mach-davinci/spl.c
@@ -36,9 +36,6 @@ void putc(char c)
 
 void spl_board_init(void)
 {
-#ifdef CONFIG_SOC_DM365
-	dm36x_lowlevel_init(0);
-#endif
 #ifdef CONFIG_SOC_DA8XX
 	arch_cpu_init();
 #endif
diff --git a/board/ait/cam_enc_4xx/Kconfig b/board/ait/cam_enc_4xx/Kconfig
deleted file mode 100644
index 64e18f4..0000000
--- a/board/ait/cam_enc_4xx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CAM_ENC_4XX
-
-config SYS_BOARD
-	default "cam_enc_4xx"
-
-config SYS_VENDOR
-	default "ait"
-
-config SYS_CONFIG_NAME
-	default "cam_enc_4xx"
-
-endif
diff --git a/board/ait/cam_enc_4xx/MAINTAINERS b/board/ait/cam_enc_4xx/MAINTAINERS
deleted file mode 100644
index d6477c6..0000000
--- a/board/ait/cam_enc_4xx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CAM_ENC_4XX BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	board/ait/cam_enc_4xx/
-F:	include/configs/cam_enc_4xx.h
-F:	configs/cam_enc_4xx_defconfig
diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile
deleted file mode 100644
index 0d03ce0..0000000
--- a/board/ait/cam_enc_4xx/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cam_enc_4xx.o
diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c
deleted file mode 100644
index 290dc19..0000000
--- a/board/ait/cam_enc_4xx/cam_enc_4xx.c
+++ /dev/null
@@ -1,1106 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <cli.h>
-#include <errno.h>
-#include <linux/mtd/nand.h>
-#include <nand.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/davinci_misc.h>
-#ifdef CONFIG_DAVINCI_MMC
-#include <mmc.h>
-#include <asm/arch/sdmmc_defs.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SPL_BUILD
-static struct davinci_timer *timer =
-	(struct davinci_timer *)DAVINCI_TIMER3_BASE;
-
-static unsigned long get_timer_val(void)
-{
-	unsigned long now = readl(&timer->tim34);
-
-	return now;
-}
-
-static int timer_running(void)
-{
-	return readl(&timer->tcr) &
-		(DV_TIMER_TCR_ENAMODE_MASK << DV_TIMER_TCR_ENAMODE34_SHIFT);
-}
-
-static void stop_timer(void)
-{
-	writel(0x0, &timer->tcr);
-	return;
-}
-
-int checkboard(void)
-{
-	printf("Board: AIT CAM ENC 4XX\n");
-	return 0;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-static int cam_enc_4xx_check_network(void)
-{
-	char *s;
-
-	s = getenv("ethaddr");
-	if (!s)
-		return -EINVAL;
-
-	if (!is_valid_ether_addr((const u8 *)s))
-		return -EINVAL;
-
-	s = getenv("ipaddr");
-	if (!s)
-		return -EINVAL;
-
-	s = getenv("netmask");
-	if (!s)
-		return -EINVAL;
-
-	s = getenv("serverip");
-	if (!s)
-		return -EINVAL;
-
-	s = getenv("gatewayip");
-	if (!s)
-		return -EINVAL;
-
-	return 0;
-}
-int board_eth_init(bd_t *bis)
-{
-	int ret;
-
-	ret = cam_enc_4xx_check_network();
-	if (ret)
-		return ret;
-
-	davinci_emac_initialize();
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-static int
-davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
-				   uint8_t *buf, int oob_required, int page)
-{
-	struct nand_chip *this = mtd->priv;
-	int i, eccsize = chip->ecc.size;
-	int eccbytes = chip->ecc.bytes;
-	int eccsteps = chip->ecc.steps;
-	uint8_t *p = buf;
-	uint8_t *oob = chip->oob_poi;
-
-	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
-
-	chip->read_buf(mtd, oob, mtd->oobsize);
-
-	chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask);
-
-
-	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-		int stat;
-
-		chip->ecc.hwctl(mtd, NAND_ECC_READ);
-		chip->read_buf(mtd, p, eccsize);
-		chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
-
-		if (chip->ecc.prepad)
-			oob += chip->ecc.prepad;
-
-		stat = chip->ecc.correct(mtd, p, oob, NULL);
-
-		if (stat == -1)
-			mtd->ecc_stats.failed++;
-		else
-			mtd->ecc_stats.corrected += stat;
-
-		oob += eccbytes;
-
-		if (chip->ecc.postpad)
-			oob += chip->ecc.postpad;
-	}
-
-	/* Calculate remaining oob bytes */
-	i = mtd->oobsize - (oob - chip->oob_poi);
-	if (i)
-		chip->read_buf(mtd, oob, i);
-
-	return 0;
-}
-
-static int davinci_std_write_page_syndrome(struct mtd_info *mtd,
-				    struct nand_chip *chip, const uint8_t *buf,
-				    int oob_required)
-{
-	unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
-	struct nand_chip *this = mtd->priv;
-	int i, eccsize = chip->ecc.size;
-	int eccbytes = chip->ecc.bytes;
-	int eccsteps = chip->ecc.steps;
-	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
-	int offset = 0;
-	const uint8_t *p = buf;
-	uint8_t *oob = chip->oob_poi;
-
-	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
-		chip->write_buf(mtd, p, eccsize);
-
-		/* Calculate ECC without prepad */
-		chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
-
-		if (chip->ecc.prepad) {
-			offset = (chip->ecc.steps - eccsteps) * chunk;
-			memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
-			oob += chip->ecc.prepad;
-		}
-
-		offset = ((chip->ecc.steps - eccsteps) * chunk) +
-				chip->ecc.prepad;
-		memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
-		oob += eccbytes;
-
-		if (chip->ecc.postpad) {
-			offset = ((chip->ecc.steps - eccsteps) * chunk) +
-					chip->ecc.prepad + eccbytes;
-			memcpy(&davinci_ecc_buf[offset], oob,
-				chip->ecc.postpad);
-			oob += chip->ecc.postpad;
-		}
-	}
-
-	/*
-	 * Write the sparebytes into the page once
-	 * all eccsteps have been covered
-	 */
-	for (i = 0; i < mtd->oobsize; i++)
-		writeb(davinci_ecc_buf[i], this->IO_ADDR_W);
-
-	/* Calculate remaining oob bytes */
-	i = mtd->oobsize - (oob - chip->oob_poi);
-	if (i)
-		chip->write_buf(mtd, oob, i);
-	return 0;
-}
-
-static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
-				   struct nand_chip *chip, int page)
-{
-	int pos, status = 0;
-	const uint8_t *bufpoi = chip->oob_poi;
-
-	pos = mtd->writesize;
-
-	chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
-
-	chip->write_buf(mtd, bufpoi, mtd->oobsize);
-
-	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
-	status = chip->waitfunc(mtd, chip);
-
-	return status & NAND_STATUS_FAIL ? -1 : 0;
-}
-
-static int davinci_std_read_oob_syndrome(struct mtd_info *mtd,
-	struct nand_chip *chip, int page)
-{
-	struct nand_chip *this = mtd->priv;
-	uint8_t *buf = chip->oob_poi;
-	uint8_t *bufpoi = buf;
-
-	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
-
-	chip->read_buf(mtd, bufpoi, mtd->oobsize);
-
-	return 0;
-}
-
-static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
-{
-	struct nand_chip	*this = mtd->priv;
-	unsigned long		wbase = (unsigned long) this->IO_ADDR_W;
-	unsigned long		rbase = (unsigned long) this->IO_ADDR_R;
-
-	if (chip == 1) {
-		__set_bit(14, &wbase);
-		__set_bit(14, &rbase);
-	} else {
-		__clear_bit(14, &wbase);
-		__clear_bit(14, &rbase);
-	}
-	this->IO_ADDR_W = (void *)wbase;
-	this->IO_ADDR_R = (void *)rbase;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	davinci_nand_init(nand);
-	nand->select_chip = nand_dm365evm_select_chip;
-
-	return 0;
-}
-
-struct nand_ecc_ctrl org_ecc;
-static int notsaved = 1;
-
-static int nand_switch_hw_func(int mode)
-{
-	struct nand_chip *nand;
-	struct mtd_info *mtd;
-
-	if (nand_curr_device < 0 ||
-	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[nand_curr_device].name) {
-		printf("Error: Can't switch hw functions," \
-			" no devices available\n");
-		return -1;
-	}
-
-	mtd = &nand_info[nand_curr_device];
-	nand = mtd->priv;
-
-	if (mode == 0) {
-		if (notsaved == 0) {
-			printf("switching to uboot hw functions.\n");
-			memcpy(&nand->ecc, &org_ecc,
-				sizeof(struct nand_ecc_ctrl));
-		}
-	} else {
-		/* RBL */
-		printf("switching to RBL hw functions.\n");
-		if (notsaved == 1) {
-			memcpy(&org_ecc, &nand->ecc,
-				sizeof(struct nand_ecc_ctrl));
-			notsaved = 0;
-		}
-		nand->ecc.mode = NAND_ECC_HW_SYNDROME;
-		nand->ecc.prepad = 6;
-		nand->ecc.read_page = davinci_std_read_page_syndrome;
-		nand->ecc.write_page = davinci_std_write_page_syndrome;
-		nand->ecc.read_oob = davinci_std_read_oob_syndrome;
-		nand->ecc.write_oob = davinci_std_write_oob_syndrome;
-	}
-	return mode;
-}
-
-static int hwmode;
-
-static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
-		char *const argv[])
-{
-	if (argc != 2)
-		goto usage;
-	if (strncmp(argv[1], "rbl", 2) == 0)
-		hwmode = nand_switch_hw_func(1);
-	else if (strncmp(argv[1], "uboot", 2) == 0)
-		hwmode = nand_switch_hw_func(0);
-	else
-		goto usage;
-
-	return 0;
-
-usage:
-	printf("Usage: nandrbl %s\n", cmdtp->usage);
-	return 1;
-}
-
-U_BOOT_CMD(
-	nandrbl, 2, 1,	do_switch_ecc,
-	"switch between rbl/uboot NAND ECC calculation algorithm",
-	"[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm"
-);
-
-
-#endif /* #ifdef CONFIG_NAND_DAVINCI */
-
-#ifdef CONFIG_DAVINCI_MMC
-static struct davinci_mmc mmc_sd0 = {
-	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
-	.input_clk	= 121500000,
-	.host_caps	= MMC_MODE_4BIT,
-	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
-	.version	= MMC_CTLR_VERSION_2,
-};
-
-int board_mmc_init(bd_t *bis)
-{
-	int err;
-
-	/* Add slot-0 to mmc subsystem */
-	err = davinci_mmc_init(bis, &mmc_sd0);
-
-	return err;
-}
-#endif
-
-int board_late_init(void)
-{
-	struct davinci_gpio *gpio = davinci_gpio_bank45;
-
-	/* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */
-	while ((get_timer_val() < CONFIG_AIT_TIMER_TIMEOUT) &&
-		timer_running())
-		;
-
-	/* 1 sec reached -> stop timer, clear all LED */
-	stop_timer();
-	clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
-	return 0;
-}
-
-void reset_phy(void)
-{
-	char *name = "GENERIC @ 0x00";
-
-	/* reset the phy */
-	miiphy_reset(name, 0x0);
-}
-
-#else /* #ifndef CONFIG_SPL_BUILD */
-static void cam_enc_4xx_set_all_led(void)
-{
-	struct davinci_gpio *gpio = davinci_gpio_bank45;
-
-	setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
-}
-
-/*
- * TIMER 0 is used for tick
- */
-static struct davinci_timer *timer =
-	(struct davinci_timer *)DAVINCI_TIMER3_BASE;
-
-#define TIMER_LOAD_VAL	0xffffffff
-#define TIM_CLK_DIV	16
-
-static int cam_enc_4xx_timer_init(void)
-{
-	/* We are using timer34 in unchained 32-bit mode, full speed */
-	writel(0x0, &timer->tcr);
-	writel(0x0, &timer->tgcr);
-	writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
-	writel(0x0, &timer->tim34);
-	writel(TIMER_LOAD_VAL, &timer->prd34);
-	writel(2 << 22, &timer->tcr);
-	return 0;
-}
-
-void board_gpio_init(void)
-{
-	struct davinci_gpio *gpio;
-
-	cam_enc_4xx_set_all_led();
-	cam_enc_4xx_timer_init();
-	gpio = davinci_gpio_bank01;
-	clrbits_le32(&gpio->dir, ~0xfdfffffe);
-	/* clear LED D14 = GPIO25 */
-	clrbits_le32(&gpio->out_data, 0x02000000);
-	gpio = davinci_gpio_bank23;
-	clrbits_le32(&gpio->dir, ~0x5ff0afef);
-	/* set GPIO61 to 1 -> intern UART0 as Console */
-	setbits_le32(&gpio->out_data, 0x20000000);
-	/*
-	 * PHY out of reset GIO 50 = 1
-	 * NAND WP off GIO 51 = 1
-	 */
-	setbits_le32(&gpio->out_data, 0x000c0004);
-	gpio = davinci_gpio_bank45;
-	clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK);
-	/*
-	 * clear LED:
-	 * D17 = GPIO86
-	 * D11 = GPIO87
-	 * GPIO88
-	 * GPIO89
-	 * D13 = GPIO90
-	 * GPIO91
-	 */
-	clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
-	gpio = davinci_gpio_bank67;
-	clrbits_le32(&gpio->dir, ~0x000007ff);
-}
-
-/*
- * functions for the post memory test.
- */
-int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
-{
-	*vstart = CONFIG_SYS_SDRAM_BASE;
-	*size = PHYS_SDRAM_1_SIZE;
-	*phys_offset = 0;
-	return 0;
-}
-
-void arch_memory_failure_handle(void)
-{
-	cam_enc_4xx_set_all_led();
-	puts("mem failure\n");
-	while (1)
-		;
-}
-#endif
-#if defined(CONFIG_MENU)
-#include "menu.h"
-
-#define MENU_EXIT		-1
-#define MENU_EXIT_BOOTCMD	-2
-#define MENU_STAY		0
-#define MENU_MAIN		1
-#define MENU_UPDATE		2
-#define MENU_NETWORK		3
-#define MENU_LOAD		4
-
-static int menu_start;
-
-#define FIT_SUBTYPE_UNKNOWN		0
-#define FIT_SUBTYPE_UBL_HEADER		1
-#define FIT_SUBTYPE_SPL_IMAGE		2
-#define FIT_SUBTYPE_UBOOT_IMAGE		3
-#define FIT_SUBTYPE_DF_ENV_IMAGE	4
-#define FIT_SUBTYPE_RAMDISK_IMAGE	5
-
-struct fit_images_info {
-	u_int8_t type;
-	int subtype;
-	char desc[200];
-	const void *data;
-	size_t size;
-};
-
-static struct fit_images_info imgs[10];
-
-struct menu_display {
-	char	title[50];
-	int	timeout; /* in sec */
-	int	id; /* MENU_* */
-	char	**menulist;
-	int (*menu_evaluate)(char *choice);
-};
-
-char *menu_main[] = {
-	"(1) Boot",
-	"(2) Update Software",
-	"(3) Reset to default setting and boot",
-	"(4) Enter U-Boot console",
-	NULL
-};
-
-char *menu_update[] = {
-	"(1) Network settings",
-	"(2) load image",
-	"(3) back to main",
-	NULL
-};
-
-char *menu_load[] = {
-	"(1) install image",
-	"(2) cancel",
-	NULL
-};
-
-char *menu_network[] = {
-	"(1) ipaddr   ",
-	"(2) netmask  ",
-	"(3) serverip ",
-	"(4) gatewayip",
-	"(5) tftp image name",
-	"(6) back to update software",
-	NULL
-};
-
-static void ait_menu_print(void *data)
-{
-	printf("%s\n", (char *)data);
-	return;
-}
-
-static char *menu_handle(struct menu_display *display)
-{
-	struct menu *m;
-	int i;
-	void *choice = NULL;
-	char key[2];
-	int ret;
-	char *s;
-	char temp[6][200];
-
-	m = menu_create(display->title, display->timeout, 1, ait_menu_print,
-			NULL, NULL);
-
-	for (i = 0; display->menulist[i]; i++) {
-		sprintf(key, "%d", i + 1);
-		if (display->id == MENU_NETWORK) {
-			switch (i) {
-			case 0:
-				s = getenv("ipaddr");
-				break;
-			case 1:
-				s = getenv("netmask");
-				break;
-			case 2:
-				s = getenv("serverip");
-				break;
-			case 3:
-				s = getenv("gatewayip");
-				break;
-			case 4:
-				s = getenv("img_file");
-				break;
-			default:
-				s = NULL;
-				break;
-			}
-			if (s) {
-				sprintf(temp[i], "%s: %s",
-					display->menulist[i], s);
-				ret = menu_item_add(m, key, temp[i]);
-			} else {
-				ret = menu_item_add(m, key,
-					display->menulist[i]);
-			}
-		} else {
-			ret = menu_item_add(m, key, display->menulist[i]);
-		}
-
-		if (ret != 1) {
-			printf("failed to add item!");
-			menu_destroy(m);
-			return NULL;
-		}
-	}
-	sprintf(key, "%d", 1);
-	menu_default_set(m, key);
-
-	if (menu_get_choice(m, &choice) != 1)
-		debug("Problem picking a choice!\n");
-
-	menu_destroy(m);
-
-	return choice;
-}
-
-static int ait_menu_show(struct menu_display *display, int bootdelay)
-{
-	int end = MENU_STAY;
-	char *choice;
-
-	if ((menu_start == 0) && (display->id == MENU_MAIN))
-		display->timeout = bootdelay;
-	else
-		display->timeout = 0;
-
-	while (end == MENU_STAY) {
-		choice = menu_handle(display);
-		if (choice)
-			end = display->menu_evaluate(choice);
-
-		if (end == display->id)
-			end = MENU_STAY;
-		if (display->id == MENU_MAIN) {
-			if (menu_start == 0)
-				end = MENU_EXIT_BOOTCMD;
-			else
-				display->timeout = 0;
-		}
-	}
-	return end;
-}
-
-static int ait_writeublheader(void)
-{
-	char s[20];
-	unsigned long i;
-	int ret;
-
-	for (i = CONFIG_SYS_NAND_BLOCK_SIZE;
-		i < CONFIG_SYS_NAND_U_BOOT_OFFS;
-		i += CONFIG_SYS_NAND_BLOCK_SIZE) {
-		sprintf(s, "%lx", i);
-		ret = setenv("header_addr", s);
-		if (ret == 0)
-			ret = run_command("run img_writeheader", 0);
-		if (ret != 0)
-			break;
-	}
-	return ret;
-}
-
-static int ait_menu_install_images(void)
-{
-	int ret = 0;
-	int count = 0;
-	char s[100];
-	char *t;
-
-	/*
-	 * possible image types:
-	 * FIT_SUBTYPE_UNKNOWN
-	 * FIT_SUBTYPE_UBL_HEADER
-	 * FIT_SUBTYPE_SPL_IMAGE
-	 * FIT_SUBTYPE_UBOOT_IMAGE
-	 * FIT_SUBTYPE_DF_ENV_IMAGE
-	 * FIT_SUBTYPE_RAMDISK_IMAGE
-	 *
-	 * use Envvariables:
-	 * img_addr_r: image start addr
-	 * header_addr: addr where to write to UBL header
-	 * img_writeheader: write ubl header to nand
-	 * img_writespl: write spl to nand
-	 * img_writeuboot: write uboot to nand
-	 * img_writedfenv: write default environment to ubi volume
-	 * img_volume: which ubi volume should be updated with img_writeramdisk
-	 * filesize: size of data for updating ubi volume
-	 * img_writeramdisk: write ramdisk to ubi volume
-	 */
-
-	while (imgs[count].type != IH_TYPE_INVALID) {
-		printf("Installing %s\n",
-			genimg_get_type_name(imgs[count].type));
-		sprintf(s, "%p", imgs[count].data);
-		setenv("img_addr_r", s);
-		sprintf(s, "%lx", (unsigned long)imgs[count].size);
-		setenv("filesize", s);
-		switch (imgs[count].subtype) {
-		case FIT_SUBTYPE_DF_ENV_IMAGE:
-			ret = run_command("run img_writedfenv", 0);
-			break;
-		case FIT_SUBTYPE_RAMDISK_IMAGE:
-			t = getenv("img_volume");
-			if (!t) {
-				ret = setenv("img_volume", "rootfs1");
-			} else {
-				/* switch to other volume */
-				if (strncmp(t, "rootfs1", 7) == 0)
-					ret = setenv("img_volume", "rootfs2");
-				else
-					ret = setenv("img_volume", "rootfs1");
-			}
-			if (ret != 0)
-				break;
-
-			ret = run_command("run img_writeramdisk", 0);
-			break;
-		case FIT_SUBTYPE_SPL_IMAGE:
-			ret = run_command("run img_writespl", 0);
-			break;
-		case FIT_SUBTYPE_UBL_HEADER:
-			ret = ait_writeublheader();
-			break;
-		case FIT_SUBTYPE_UBOOT_IMAGE:
-			ret = run_command("run img_writeuboot", 0);
-			break;
-		default:
-			/* not supported type */
-			break;
-		}
-		count++;
-	}
-	/* now save dvn_* and img_volume env vars to new values */
-	if (ret == 0) {
-		t = getenv("x_dvn_boot_vers");
-		if (t)
-			setenv("dvn_boot_vers", t);
-
-		t = getenv("x_dvn_app_vers");
-		if (t)
-			setenv("dvn_boot_vers", t);
-
-		setenv("x_dvn_boot_vers", NULL);
-		setenv("x_dvn_app_vers", NULL);
-		ret = run_command("run savenewvers", 0);
-	}
-
-	return ret;
-}
-
-static int ait_menu_evaluate_load(char *choice)
-{
-	if (!choice)
-		return -1;
-
-	switch (choice[1]) {
-	case '1':
-		/* install image */
-		ait_menu_install_images();
-		break;
-	case '2':
-		/* cancel, back to main */
-		setenv("x_dvn_boot_vers", NULL);
-		setenv("x_dvn_app_vers", NULL);
-		break;
-	}
-
-	return MENU_MAIN;
-}
-
-struct menu_display ait_load = {
-	.title = "AIT load image",
-	.timeout = 0,
-	.id = MENU_LOAD,
-	.menulist = menu_load,
-	.menu_evaluate = ait_menu_evaluate_load,
-};
-
-static void ait_menu_read_env(char *name)
-{
-	char output[CONFIG_SYS_CBSIZE];
-	char cbuf[CONFIG_SYS_CBSIZE];
-	int readret;
-	int ret;
-
-	sprintf(output, "%s old: %s value: ", name, getenv(name));
-	memset(cbuf, 0, CONFIG_SYS_CBSIZE);
-	readret = cli_readline_into_buffer(output, cbuf, 0);
-
-	if (readret >= 0) {
-		ret = setenv(name, cbuf);
-		if (ret) {
-			printf("Error setting %s\n", name);
-			return;
-		}
-	}
-	return;
-}
-
-static int ait_menu_evaluate_network(char *choice)
-{
-	if (!choice)
-		return MENU_MAIN;
-
-	switch (choice[1]) {
-	case '1':
-		ait_menu_read_env("ipaddr");
-		break;
-	case '2':
-		ait_menu_read_env("netmask");
-		break;
-	case '3':
-		ait_menu_read_env("serverip");
-		break;
-	case '4':
-		ait_menu_read_env("gatewayip");
-		break;
-	case '5':
-		ait_menu_read_env("img_file");
-		break;
-	case '6':
-		return MENU_UPDATE;
-		break;
-	}
-
-	return MENU_STAY;
-}
-
-struct menu_display ait_network = {
-	.title = "AIT network settings",
-	.timeout = 0,
-	.id = MENU_NETWORK,
-	.menulist = menu_network,
-	.menu_evaluate = ait_menu_evaluate_network,
-};
-
-static int fit_get_subtype(const void *fit, int noffset, char **subtype)
-{
-	int len;
-
-	*subtype = (char *)fdt_getprop(fit, noffset, "subtype", &len);
-	if (*subtype == NULL)
-		return -1;
-
-	return 0;
-}
-
-static int ait_subtype_nr(char *subtype)
-{
-	int ret = FIT_SUBTYPE_UNKNOWN;
-
-	if (!strncmp("ublheader", subtype, strlen("ublheader")))
-		return FIT_SUBTYPE_UBL_HEADER;
-	if (!strncmp("splimage", subtype, strlen("splimage")))
-		return FIT_SUBTYPE_SPL_IMAGE;
-	if (!strncmp("ubootimage", subtype, strlen("ubootimage")))
-		return FIT_SUBTYPE_UBOOT_IMAGE;
-	if (!strncmp("dfenvimage", subtype, strlen("dfenvimage")))
-		return FIT_SUBTYPE_DF_ENV_IMAGE;
-
-	return ret;
-}
-
-static int ait_menu_check_image(void)
-{
-	char *s;
-	unsigned long fit_addr;
-	void *addr;
-	int format;
-	char *desc;
-	char *subtype;
-	int images_noffset;
-	int noffset;
-	int ndepth;
-	int count = 0;
-	int ret;
-	int i;
-	int found_uboot = -1;
-	int found_ramdisk = -1;
-
-	memset(imgs, 0, sizeof(imgs));
-	s = getenv("fit_addr_r");
-	fit_addr = s ? (unsigned long)simple_strtol(s, NULL, 16) : \
-			CONFIG_BOARD_IMG_ADDR_R;
-
-	addr = (void *)fit_addr;
-	/* check if it is a FIT image */
-	format = genimg_get_format(addr);
-	if (format != IMAGE_FORMAT_FIT)
-		return -EINVAL;
-
-	if (!fit_check_format(addr))
-		return -EINVAL;
-
-	/* print the FIT description */
-	ret = fit_get_desc(addr, 0, &desc);
-	printf("FIT description: ");
-	if (ret)
-		printf("unavailable\n");
-	else
-		printf("%s\n", desc);
-
-	/* find images */
-	images_noffset = fdt_path_offset(addr, FIT_IMAGES_PATH);
-	if (images_noffset < 0) {
-		printf("Can't find images parent node '%s' (%s)\n",
-			FIT_IMAGES_PATH, fdt_strerror(images_noffset));
-		return -EINVAL;
-	}
-
-	/* Process its subnodes, print out component images details */
-	for (ndepth = 0, count = 0,
-		noffset = fdt_next_node(addr, images_noffset, &ndepth);
-		(noffset >= 0) && (ndepth > 0);
-		noffset = fdt_next_node(addr, noffset, &ndepth)) {
-		if (ndepth == 1) {
-			/*
-			 * Direct child node of the images parent node,
-			 * i.e. component image node.
-			 */
-			printf("Image %u (%s)\n", count,
-					fit_get_name(addr, noffset, NULL));
-
-			fit_image_print(addr, noffset, "");
-
-			fit_image_get_type(addr, noffset,
-				&imgs[count].type);
-			/* Mandatory properties */
-			ret = fit_get_desc(addr, noffset, &desc);
-			printf("Description:  ");
-			if (ret)
-				printf("unavailable\n");
-			else
-				printf("%s\n", desc);
-
-			ret = fit_get_subtype(addr, noffset, &subtype);
-			printf("Subtype:  ");
-			if (ret) {
-				printf("unavailable\n");
-			} else {
-				imgs[count].subtype = ait_subtype_nr(subtype);
-				printf("%s %d\n", subtype,
-					imgs[count].subtype);
-			}
-
-			sprintf(imgs[count].desc, "%s", desc);
-
-			ret = fit_image_get_data(addr, noffset,
-				&imgs[count].data,
-				&imgs[count].size);
-
-			printf("Data Size:    ");
-			if (ret)
-				printf("unavailable\n");
-			else
-				genimg_print_size(imgs[count].size);
-			printf("Data @ %p\n", imgs[count].data);
-			count++;
-		}
-	}
-
-	for (i = 0; i < count; i++) {
-		if (imgs[i].subtype == FIT_SUBTYPE_UBOOT_IMAGE)
-			found_uboot = i;
-		if (imgs[i].type == IH_TYPE_RAMDISK) {
-			found_ramdisk = i;
-			imgs[i].subtype = FIT_SUBTYPE_RAMDISK_IMAGE;
-		}
-	}
-
-	/* dvn_* env var update, if the FIT descriptors are different */
-	if (found_uboot >= 0) {
-		s = getenv("dvn_boot_vers");
-		if (s) {
-			ret = strcmp(s, imgs[found_uboot].desc);
-			if (ret != 0) {
-				setenv("x_dvn_boot_vers",
-					imgs[found_uboot].desc);
-			} else {
-				found_uboot = -1;
-				printf("no new uboot version\n");
-			}
-		} else {
-			setenv("dvn_boot_vers", imgs[found_uboot].desc);
-		}
-	}
-	if (found_ramdisk >= 0) {
-		s = getenv("dvn_app_vers");
-		if (s) {
-			ret = strcmp(s, imgs[found_ramdisk].desc);
-			if (ret != 0) {
-				setenv("x_dvn_app_vers",
-					imgs[found_ramdisk].desc);
-			} else {
-				found_ramdisk = -1;
-				printf("no new ramdisk version\n");
-			}
-		} else {
-			setenv("dvn_app_vers", imgs[found_ramdisk].desc);
-		}
-	}
-	if ((found_uboot == -1) && (found_ramdisk == -1))
-		return -EINVAL;
-
-	return 0;
-}
-
-static int ait_menu_evaluate_update(char *choice)
-{
-	int ret;
-
-	if (!choice)
-		return MENU_MAIN;
-
-	switch (choice[1]) {
-	case '1':
-		return ait_menu_show(&ait_network, 0);
-		break;
-	case '2':
-		/* load image */
-		ret = run_command("run load_img", 0);
-		printf("ret: %d\n", ret);
-		if (ret)
-			return MENU_UPDATE;
-
-		ret = ait_menu_check_image();
-		if (ret)
-			return MENU_UPDATE;
-
-		return ait_menu_show(&ait_load, 0);
-		break;
-	case '3':
-		return MENU_MAIN;
-		break;
-
-	}
-
-	return MENU_MAIN;
-}
-
-struct menu_display ait_update = {
-	.title = "AIT Update Software",
-	.timeout = 0,
-	.id = MENU_UPDATE,
-	.menulist = menu_update,
-	.menu_evaluate = ait_menu_evaluate_update,
-};
-
-static int ait_menu_evaluate_main(char *choice)
-{
-	if (!choice)
-		return MENU_STAY;
-
-	menu_start = 1;
-	switch (choice[1]) {
-	case '1':
-		/* run bootcmd */
-		return MENU_EXIT_BOOTCMD;
-		break;
-	case '2':
-		return ait_menu_show(&ait_update, 0);
-		break;
-	case '3':
-		/* reset to default settings */
-		setenv("app_reset", "yes");
-		return MENU_EXIT_BOOTCMD;
-		break;
-	case '4':
-		/* u-boot shell */
-		return MENU_EXIT;
-		break;
-	}
-
-	return MENU_EXIT;
-}
-
-struct menu_display ait_main = {
-	.title = "AIT Main",
-	.timeout = CONFIG_BOOTDELAY,
-	.id = MENU_MAIN,
-	.menulist = menu_main,
-	.menu_evaluate = ait_menu_evaluate_main,
-};
-
-int menu_show(int bootdelay)
-{
-	int ret;
-
-	run_command("run saveparms", 0);
-	ret = ait_menu_show(&ait_main, bootdelay);
-	run_command("run restoreparms", 0);
-
-	if (ret == MENU_EXIT_BOOTCMD)
-		return 0;
-
-	return MENU_EXIT;
-}
-
-void menu_display_statusline(struct menu *m)
-{
-	char *s1, *s2;
-
-	s1 = getenv("x_dvn_boot_vers");
-	if (!s1)
-		s1 = getenv("dvn_boot_vers");
-
-	s2 = getenv("x_dvn_app_vers");
-	if (!s2)
-		s2 = getenv("dvn_app_vers");
-
-	printf("State: dvn_boot_vers: %s dvn_app_vers: %s\n", s1, s2);
-	return;
-}
-#endif
diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk
deleted file mode 100644
index 2022151..0000000
--- a/board/ait/cam_enc_4xx/config.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# 	AIT cam_enc_4xx board
-#	cam_enc_4xx board has 1 bank of 256 MB DDR RAM
-#	Physical Address: 8000'0000 to 9000'0000
-#
-# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-
-UBL_CONFIG = $(srctree)/board/$(BOARDDIR)/ublimage.cfg
-ifndef CONFIG_SPL_BUILD
-ALL-y += u-boot.ubl
-else
-# as SPL_TEXT_BASE is not page-aligned, we need for some
-# linkers the -n flag (Do not page align data), to prevent
-# the following error message:
-# arm-linux-ld: u-boot-spl: Not enough room for program headers, try linking
-# with -N
-LDFLAGS_u-boot-spl += -n
-endif
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
deleted file mode 100644
index f5c19df..0000000
--- a/board/ait/cam_enc_4xx/u-boot-spl.lds
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
-		LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = CONFIG_SPL_TEXT_BASE;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	__start = .;
-	  *(.vectors)
-	  arch/arm/cpu/arm926ejs/start.o	(.text*)
-	  *(.text*)
-	} >.sram
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
-	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-	. = ALIGN(4);
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	} >.sram
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start = .;
-		*(.bss*)
-		. = ALIGN(4);
-		__bss_end = .;
-	} >.sram
-
-	__image_copy_end = .;
-
-	.end :
-	{
-		*(.__end)
-	}
-}
diff --git a/board/ait/cam_enc_4xx/ublimage.cfg b/board/ait/cam_enc_4xx/ublimage.cfg
deleted file mode 100644
index d4fe705..0000000
--- a/board/ait/cam_enc_4xx/ublimage.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C Copyright 2011
-# Heiko Schocher DENX Software Engineering hs@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# Refer doc/README.ublimage for more details about how-to configure
-# and create ublimage boot image
-#
-# The syntax is taken as close as possible with the kwbimage
-
-# UBL special mode : one of
-# safe (the board has no nand neither onenand)
-MODE	safe
-
-# Entry point address for the user bootloader (absolute address)
-# nand spl TEXT_BASE = 0x20 !!
-ENTRY	0x00000020
-
-# Number of pages (size of user bootloader in number of pages)
-# @ nand spl 6 pages
-PAGES	6
-
-# Block number where user bootloader is present
-START_BLOCK	0
-
-# Page number where user bootloader is present
-# Page 0 is always UBL header
-START_PAGE	0
-
-LD_ADDR		0x20
diff --git a/board/davinci/dm355evm/Kconfig b/board/davinci/dm355evm/Kconfig
deleted file mode 100644
index ec2c276..0000000
--- a/board/davinci/dm355evm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_DM355EVM
-
-config SYS_BOARD
-	default "dm355evm"
-
-config SYS_VENDOR
-	default "davinci"
-
-config SYS_CONFIG_NAME
-	default "davinci_dm355evm"
-
-endif
diff --git a/board/davinci/dm355evm/MAINTAINERS b/board/davinci/dm355evm/MAINTAINERS
deleted file mode 100644
index c017e09..0000000
--- a/board/davinci/dm355evm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DM355EVM BOARD
-#M:	Sandeep Paulraj <s-paulraj@ti.com>
-S:	Orphan (since 2014-08)
-F:	board/davinci/dm355evm/
-F:	include/configs/davinci_dm355evm.h
-F:	configs/davinci_dm355evm_defconfig
diff --git a/board/davinci/dm355evm/Makefile b/board/davinci/dm355evm/Makefile
deleted file mode 100644
index bcb7e6f..0000000
--- a/board/davinci/dm355evm/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= dm355evm.o
diff --git a/board/davinci/dm355evm/config.mk b/board/davinci/dm355evm/config.mk
deleted file mode 100644
index 9a06300..0000000
--- a/board/davinci/dm355evm/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Spectrum Digital DM355 EVM board
-#	dm355evm board has 1 bank of 128 MB DDR RAM
-#	Physical Address: 8000'0000 to 8800'0000
-#
-# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c
deleted file mode 100644
index e5a958f..0000000
--- a/board/davinci/dm355evm/dm355evm.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/davinci_misc.h>
-#include <net.h>
-#include <netdev.h>
-#ifdef CONFIG_DAVINCI_MMC
-#include <mmc.h>
-#include <asm/arch/sdmmc_defs.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * With the DM355 EVM, u-boot is *always* a third stage loader,
- * unless a JTAG debugger handles the first two stages:
- *
- *   - 1st stage is ROM Boot Loader (RBL), which searches for a
- *     second stage loader in one of three places based on SW7:
- *     NAND (with MMC/SD fallback), MMC/SD, or UART.
- *
- *   - 2nd stage is User Boot Loader (UBL), using at most 30KB
- *     of on-chip SRAM, responsible for lowlevel init, and for
- *     loading the third stage loader into DRAM.
- *
- *   - 3rd stage, that's us!
- */
-
-int board_init(void)
-{
-	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	/* We expect the UBL to have handled "lowlevel init", which
-	 * involves setting up at least:
-	 *  - clocks
-	 *      + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
-	 *      + clock divisors for those PLLs
-	 *      + LPSC_DDR module enabled
-	 *      + LPSC_TIMER0 module (still) enabled
-	 *  - EMIF
-	 *      + DDR init and timings
-	 *      + AEMIF timings (for NAND and DM9000)
-	 *  - pinmux
-	 *
-	 * Some of that is repeated here, mostly as a precaution.
-	 */
-
-	/* AEMIF:  Some "address" lines are available as GPIOs.  A3..A13
-	 * could be too if we used A12 as a GPIO during NAND chipselect
-	 * (and Linux did too), letting us control the LED on A7/GPIO61.
-	 */
-	REG(PINMUX2) = 0x0c08;
-
-	/* UART0 may still be in SyncReset if we didn't boot from UART */
-	davinci_enable_uart0();
-
-	/* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
-	lpsc_on(DAVINCI_LPSC_TPCC);
-	lpsc_on(DAVINCI_LPSC_TPTC0);
-	lpsc_on(DAVINCI_LPSC_TPTC1);
-
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
-	return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-
-static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
-{
-	struct nand_chip	*this = mtd->priv;
-	unsigned long		wbase = (unsigned long) this->IO_ADDR_W;
-	unsigned long		rbase = (unsigned long) this->IO_ADDR_R;
-
-	if (chip == 1) {
-		__set_bit(14, &wbase);
-		__set_bit(14, &rbase);
-	} else {
-		__clear_bit(14, &wbase);
-		__clear_bit(14, &rbase);
-	}
-	this->IO_ADDR_W = (void *)wbase;
-	this->IO_ADDR_R = (void *)rbase;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	davinci_nand_init(nand);
-	nand->select_chip = nand_dm355evm_select_chip;
-	return 0;
-}
-
-#endif
-
-#ifdef CONFIG_DAVINCI_MMC
-static struct davinci_mmc mmc_sd0 = {
-	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
-	.input_clk	= 108000000,
-	.host_caps	= MMC_MODE_4BIT,
-	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
-	.version	= MMC_CTLR_VERSION_1,
-};
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
-static struct davinci_mmc mmc_sd1 = {
-	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
-	.input_clk	= 108000000,
-	.host_caps	= MMC_MODE_4BIT,
-	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
-	.version	= MMC_CTLR_VERSION_1,
-};
-#endif
-
-int board_mmc_init(bd_t *bis)
-{
-	int err;
-
-	/* Add slot-0 to mmc subsystem */
-	err = davinci_mmc_init(bis, &mmc_sd0);
-	if (err)
-		return err;
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
-	/* Add slot-1 to mmc subsystem */
-	err = davinci_mmc_init(bis, &mmc_sd1);
-#endif
-
-	return err;
-}
-#endif
diff --git a/board/davinci/dm355leopard/Kconfig b/board/davinci/dm355leopard/Kconfig
deleted file mode 100644
index ab4230a..0000000
--- a/board/davinci/dm355leopard/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_DM355LEOPARD
-
-config SYS_BOARD
-	default "dm355leopard"
-
-config SYS_VENDOR
-	default "davinci"
-
-config SYS_CONFIG_NAME
-	default "davinci_dm355leopard"
-
-endif
diff --git a/board/davinci/dm355leopard/MAINTAINERS b/board/davinci/dm355leopard/MAINTAINERS
deleted file mode 100644
index ed04d43..0000000
--- a/board/davinci/dm355leopard/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DM355LEOPARD BOARD
-#M:	Sandeep Paulraj <s-paulraj@ti.com>
-S:	Orphan (since 2014-08)
-F:	board/davinci/dm355leopard/
-F:	include/configs/davinci_dm355leopard.h
-F:	configs/davinci_dm355leopard_defconfig
diff --git a/board/davinci/dm355leopard/Makefile b/board/davinci/dm355leopard/Makefile
deleted file mode 100644
index 7035429..0000000
--- a/board/davinci/dm355leopard/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= dm355leopard.o
diff --git a/board/davinci/dm355leopard/config.mk b/board/davinci/dm355leopard/config.mk
deleted file mode 100644
index 28ff3f3..0000000
--- a/board/davinci/dm355leopard/config.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c
deleted file mode 100644
index 53902f9..0000000
--- a/board/davinci/dm355leopard/dm355leopard.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/davinci_misc.h>
-#include <net.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	struct davinci_gpio *gpio01_base =
-			(struct davinci_gpio *)DAVINCI_GPIO_BANK01;
-	struct davinci_gpio *gpio23_base =
-			(struct davinci_gpio *)DAVINCI_GPIO_BANK23;
-	struct davinci_gpio *gpio67_base =
-			(struct davinci_gpio *)DAVINCI_GPIO_BANK67;
-
-	gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	/* GIO 9 & 10 are used for IO */
-	writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
-
-	/* Interrupt set GIO 9 */
-	writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
-
-	/* set GIO 9 input */
-	writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
-
-	/* Both edge trigger GIO 9 */
-	writel((readl(&gpio01_base->set_rising) | (1 << 9)),
-						&gpio01_base->set_rising);
-	writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
-
-	/* output low */
-	writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
-						&gpio01_base->set_data);
-
-	/* set GIO 10 output */
-	writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
-
-	/* output high */
-	writel((readl(&gpio01_base->set_data) | (1 << 10)),
-						&gpio01_base->set_data);
-
-	/* set GIO 32 output */
-	writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
-
-	/* output High */
-	writel((readl(&gpio23_base->set_data) | (1 << 0)),
-						&gpio23_base->set_data);
-
-	/* Enable UART1 MUX Lines */
-	writel((readl(PINMUX0) & ~3), PINMUX0);
-	writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
-	writel((readl(&gpio67_base->set_data) | (1 << 6)),
-						&gpio67_base->set_data);
-
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
-	return dm9000_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
-	davinci_nand_init(nand);
-
-	return 0;
-}
-#endif
diff --git a/board/davinci/dm365evm/Kconfig b/board/davinci/dm365evm/Kconfig
deleted file mode 100644
index 724c7b6..0000000
--- a/board/davinci/dm365evm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_DM365EVM
-
-config SYS_BOARD
-	default "dm365evm"
-
-config SYS_VENDOR
-	default "davinci"
-
-config SYS_CONFIG_NAME
-	default "davinci_dm365evm"
-
-endif
diff --git a/board/davinci/dm365evm/MAINTAINERS b/board/davinci/dm365evm/MAINTAINERS
deleted file mode 100644
index 97c3ed3..0000000
--- a/board/davinci/dm365evm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DM365EVM BOARD
-#M:	Sandeep Paulraj <s-paulraj@ti.com>
-S:	Orphan (since 2014-08)
-F:	board/davinci/dm365evm/
-F:	include/configs/davinci_dm365evm.h
-F:	configs/davinci_dm365evm_defconfig
diff --git a/board/davinci/dm365evm/Makefile b/board/davinci/dm365evm/Makefile
deleted file mode 100644
index d35d81c..0000000
--- a/board/davinci/dm365evm/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= dm365evm.o
diff --git a/board/davinci/dm365evm/config.mk b/board/davinci/dm365evm/config.mk
deleted file mode 100644
index 7b1e900..0000000
--- a/board/davinci/dm365evm/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Spectrum Digital DM365 EVM board
-#	DM365 EVM board has 1 bank of 128 MB DDR RAM
-#	Physical Address: 8000'0000 to 8800'0000
-#
-# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c
deleted file mode 100644
index 24bec56..0000000
--- a/board/davinci/dm365evm/dm365evm.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/gpio.h>
-#include <netdev.h>
-#include <asm/arch/davinci_misc.h>
-#ifdef CONFIG_DAVINCI_MMC
-#include <mmc.h>
-#include <asm/arch/sdmmc_defs.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-int board_eth_init(bd_t *bis)
-{
-	uint8_t eeprom_enetaddr[6];
-	int i;
-	struct davinci_gpio *gpio1_base =
-			(struct davinci_gpio *)DAVINCI_GPIO_BANK01;
-
-	/* Configure PINMUX 3 to enable EMAC pins */
-	writel((readl(PINMUX3) | 0x1affff), PINMUX3);
-
-	/* Configure GPIO20 as output */
-	writel((readl(&gpio1_base->dir) & ~(1 << 20)), &gpio1_base->dir);
-
-	/* Toggle GPIO 20 */
-	for (i = 0; i < 20; i++) {
-		/* GPIO 20 low */
-		writel((readl(&gpio1_base->out_data) & ~(1 << 20)),
-						&gpio1_base->out_data);
-
-		udelay(1000);
-
-		/* GPIO 20 high */
-		writel((readl(&gpio1_base->out_data) | (1 << 20)),
-						&gpio1_base->out_data);
-	}
-
-	/* Configure I2C pins so that EEPROM can be read */
-	writel((readl(PINMUX3) | 0x01400000), PINMUX3);
-
-	/* Read Ethernet MAC address from EEPROM */
-	if (dvevm_read_mac_address(eeprom_enetaddr))
-		davinci_sync_env_enetaddr(eeprom_enetaddr);
-
-	davinci_emac_initialize();
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
-{
-	struct nand_chip	*this = mtd->priv;
-	unsigned long		wbase = (unsigned long) this->IO_ADDR_W;
-	unsigned long		rbase = (unsigned long) this->IO_ADDR_R;
-
-	if (chip == 1) {
-		__set_bit(14, &wbase);
-		__set_bit(14, &rbase);
-	} else {
-		__clear_bit(14, &wbase);
-		__clear_bit(14, &rbase);
-	}
-	this->IO_ADDR_W = (void *)wbase;
-	this->IO_ADDR_R = (void *)rbase;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	davinci_nand_init(nand);
-	nand->select_chip = nand_dm365evm_select_chip;
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_DAVINCI_MMC
-static struct davinci_mmc mmc_sd0 = {
-	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
-	.input_clk	= 121500000,
-	.host_caps	= MMC_MODE_4BIT,
-	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
-	.version	= MMC_CTLR_VERSION_2,
-};
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
-static struct davinci_mmc mmc_sd1 = {
-	.reg_base	= (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
-	.input_clk	= 121500000,
-	.host_caps	= MMC_MODE_4BIT,
-	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
-	.version	= MMC_CTLR_VERSION_2,
-};
-#endif
-
-int board_mmc_init(bd_t *bis)
-{
-	int err;
-
-	/* Add slot-0 to mmc subsystem */
-	err = davinci_mmc_init(bis, &mmc_sd0);
-	if (err)
-		return err;
-
-#ifdef CONFIG_DAVINCI_MMC_SD1
-#define PUPDCTL1		0x01c4007c
-	/* PINMUX(4)-DAT0-3/CMD;  PINMUX(0)-CLK */
-	writel((readl(PINMUX4) | 0x55400000), PINMUX4);
-	writel((readl(PINMUX0) | 0x00010000), PINMUX0);
-
-	/* Configure MMC/SD pins as pullup */
-	writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1);
-
-	/* Add slot-1 to mmc subsystem */
-	err = davinci_mmc_init(bis, &mmc_sd1);
-#endif
-
-	return err;
-}
-#endif
diff --git a/board/davinci/dm6467evm/Kconfig b/board/davinci/dm6467evm/Kconfig
deleted file mode 100644
index 56d2ab4..0000000
--- a/board/davinci/dm6467evm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_DM6467EVM
-
-config SYS_BOARD
-	default "dm6467evm"
-
-config SYS_VENDOR
-	default "davinci"
-
-config SYS_CONFIG_NAME
-	default "davinci_dm6467evm"
-
-endif
diff --git a/board/davinci/dm6467evm/MAINTAINERS b/board/davinci/dm6467evm/MAINTAINERS
deleted file mode 100644
index 8ca53c4..0000000
--- a/board/davinci/dm6467evm/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-DM6467EVM BOARD
-#M:	Sandeep Paulraj <s-paulraj@ti.com>
-S:	Orphan (since 2014-08)
-F:	board/davinci/dm6467evm/
-F:	include/configs/davinci_dm6467evm.h
-F:	configs/davinci_dm6467evm_defconfig
-F:	configs/davinci_dm6467Tevm_defconfig
diff --git a/board/davinci/dm6467evm/Makefile b/board/davinci/dm6467evm/Makefile
deleted file mode 100644
index acbbdd5..0000000
--- a/board/davinci/dm6467evm/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= dm6467evm.o
diff --git a/board/davinci/dm6467evm/config.mk b/board/davinci/dm6467evm/config.mk
deleted file mode 100644
index 3751043..0000000
--- a/board/davinci/dm6467evm/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c
deleted file mode 100644
index e51cc9e..0000000
--- a/board/davinci/dm6467evm/dm6467evm.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define REV_DM6467EVM		0
-#define REV_DM6467TEVM		1
-/*
- * get_board_rev() - setup to pass kernel board revision information
- * Returns:
- * bit[0-3]	System clock frequency
- * 0000b	- 27 MHz
- * 0001b	- 33 MHz
- */
-u32 get_board_rev(void)
-{
-
-#ifdef CONFIG_DAVINCI_DM6467TEVM
-	return REV_DM6467TEVM;
-#else
-	return REV_DM6467EVM;
-#endif
-
-}
-
-int board_init(void)
-{
-	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	lpsc_on(DAVINCI_DM646X_LPSC_TIMER0);
-	lpsc_on(DAVINCI_DM646X_LPSC_UART0);
-	lpsc_on(DAVINCI_DM646X_LPSC_I2C);
-	lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
-
-	/* Enable GIO3.3V cells used for EMAC */
-	REG(VDD3P3V_PWDN) = 0x80000c0;
-
-	/* Select UART function on UART0 */
-	REG(PINMUX0) &= ~(0x0000003f << 18);
-	REG(PINMUX1) &= ~(0x00000003);
-
-	return 0;
-}
-
-#if defined(CONFIG_DRIVER_TI_EMAC)
-
-int board_eth_init(bd_t *bis)
-{
-	if (!davinci_emac_initialize()) {
-		printf("Error: Ethernet init failed!\n");
-		return -1;
-	}
-
-	return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
-	davinci_nand_init(nand);
-
-	return 0;
-}
-#endif
diff --git a/board/davinci/dvevm/Kconfig b/board/davinci/dvevm/Kconfig
deleted file mode 100644
index 3f0ef82..0000000
--- a/board/davinci/dvevm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_DVEVM
-
-config SYS_BOARD
-	default "dvevm"
-
-config SYS_VENDOR
-	default "davinci"
-
-config SYS_CONFIG_NAME
-	default "davinci_dvevm"
-
-endif
diff --git a/board/davinci/dvevm/MAINTAINERS b/board/davinci/dvevm/MAINTAINERS
deleted file mode 100644
index a718b90..0000000
--- a/board/davinci/dvevm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DVEVM BOARD
-#M:	-
-S:	Maintained
-F:	board/davinci/dvevm/
-F:	include/configs/davinci_dvevm.h
-F:	configs/davinci_dvevm_defconfig
diff --git a/board/davinci/dvevm/Makefile b/board/davinci/dvevm/Makefile
deleted file mode 100644
index 7ade325..0000000
--- a/board/davinci/dvevm/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= dvevm.o
-obj-y	+= board_init.o
diff --git a/board/davinci/dvevm/board_init.S b/board/davinci/dvevm/board_init.S
deleted file mode 100644
index ded0590..0000000
--- a/board/davinci/dvevm/board_init.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-
-.globl	dv_board_init
-dv_board_init:
-
-	mov	pc, lr
diff --git a/board/davinci/dvevm/config.mk b/board/davinci/dvevm/config.mk
deleted file mode 100644
index ed80707..0000000
--- a/board/davinci/dvevm/config.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Swaminathan <swami.iyer@ti.com>
-#
-# Davinci EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Davinci EVM has 1 bank of 256 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 9000'0000
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# Visioneering Corp. Sonata board (ARM926EJS) cpu
-#
-# Sonata board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
-#
-# Schmoogie board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# we load ourself to 8108 '0000
-#
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c
deleted file mode 100644
index c34bde4..0000000
--- a/board/davinci/dvevm/dvevm.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	/* arch number of the board */
-	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
-
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-	/* Configure AEMIF pins (although this should be configured at boot time
-	 * with pull-up/pull-down resistors) */
-	REG(PINMUX0) = 0x00000c1f;
-
-	davinci_errata_workarounds();
-
-	/* Power on required peripherals */
-	lpsc_on(DAVINCI_LPSC_GPIO);
-	lpsc_on(DAVINCI_LPSC_USB);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-	/* Powerup the DSP */
-	dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-	davinci_enable_uart0();
-	davinci_enable_emac();
-	davinci_enable_i2c();
-
-	lpsc_on(DAVINCI_LPSC_TIMER1);
-	timer_init();
-
-	return(0);
-}
-
-int misc_init_r(void)
-{
-	uint8_t video_mode;
-	uint8_t eeprom_enetaddr[6];
-
-	/* Read Ethernet MAC address from EEPROM if available. */
-	if (dvevm_read_mac_address(eeprom_enetaddr))
-		davinci_sync_env_enetaddr(eeprom_enetaddr);
-
-	i2c_read(0x39, 0x00, 1, &video_mode, 1);
-
-	setenv("videostd", ((video_mode & 0x80) ? "pal" : "ntsc"));
-
-	return(0);
-}
-
-#ifdef CONFIG_USB_DAVINCI
-
-/* IO Expander I2C address and USB VBUS enable mask */
-#define IOEXP_I2C_ADDR 0x3A
-#define IOEXP_VBUSEN_MASK 1
-
-/*
- * This function enables USB VBUS by writting to IO expander using I2C.
- * Note that the I2C is already initialized at this stage. This
- * function is used by davinci specific USB wrapper code.
- */
-void enable_vbus(void)
-{
-	uchar data;  /* IO Expander data to enable VBUS */
-
-	/* Write to IO expander to enable VBUS */
-	i2c_read(IOEXP_I2C_ADDR, 0, 0, &data, 1);
-	data &= ~IOEXP_VBUSEN_MASK;
-	i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1);
-}
-#endif
diff --git a/board/davinci/schmoogie/Kconfig b/board/davinci/schmoogie/Kconfig
deleted file mode 100644
index 3581075..0000000
--- a/board/davinci/schmoogie/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_SCHMOOGIE
-
-config SYS_BOARD
-	default "schmoogie"
-
-config SYS_VENDOR
-	default "davinci"
-
-config SYS_CONFIG_NAME
-	default "davinci_schmoogie"
-
-endif
diff --git a/board/davinci/schmoogie/MAINTAINERS b/board/davinci/schmoogie/MAINTAINERS
deleted file mode 100644
index 808e7fc..0000000
--- a/board/davinci/schmoogie/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SCHMOOGIE BOARD
-#M:	-
-S:	Maintained
-F:	board/davinci/schmoogie/
-F:	include/configs/davinci_schmoogie.h
-F:	configs/davinci_schmoogie_defconfig
diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile
deleted file mode 100644
index e170d55..0000000
--- a/board/davinci/schmoogie/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= schmoogie.o
-obj-y	+= board_init.o
diff --git a/board/davinci/schmoogie/board_init.S b/board/davinci/schmoogie/board_init.S
deleted file mode 100644
index ded0590..0000000
--- a/board/davinci/schmoogie/board_init.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-
-.globl	dv_board_init
-dv_board_init:
-
-	mov	pc, lr
diff --git a/board/davinci/schmoogie/config.mk b/board/davinci/schmoogie/config.mk
deleted file mode 100644
index ed80707..0000000
--- a/board/davinci/schmoogie/config.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Swaminathan <swami.iyer@ti.com>
-#
-# Davinci EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Davinci EVM has 1 bank of 256 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 9000'0000
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# Visioneering Corp. Sonata board (ARM926EJS) cpu
-#
-# Sonata board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
-#
-# Schmoogie board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# we load ourself to 8108 '0000
-#
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c
deleted file mode 100644
index 741afc4..0000000
--- a/board/davinci/schmoogie/schmoogie.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-	/* Configure AEMIF pins (although this should be configured at boot time
-	 * with pull-up/pull-down resistors) */
-	REG(PINMUX0) = 0x00000c1f;
-
-	davinci_errata_workarounds();
-
-	/* Power on required peripherals */
-	lpsc_on(DAVINCI_LPSC_GPIO);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-	/* Powerup the DSP */
-	dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-	davinci_enable_uart0();
-	davinci_enable_emac();
-	davinci_enable_i2c();
-
-	lpsc_on(DAVINCI_LPSC_TIMER1);
-	timer_init();
-
-	return(0);
-}
-
-int misc_init_r(void)
-{
-	u_int8_t	tmp[20], buf[10];
-	int		i = 0;
-
-	/* Set serial number from UID chip */
-	const u_int8_t	crc_tbl[256] = {
-			0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
-			0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
-			0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
-			0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
-			0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
-			0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
-			0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
-			0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
-			0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
-			0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
-			0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
-			0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
-			0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
-			0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
-			0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
-			0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
-			0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
-			0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
-			0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
-			0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
-			0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
-			0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
-			0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
-			0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
-			0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
-			0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
-			0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
-			0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
-			0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
-			0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
-			0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
-			0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
-		};
-
-	/* Set serial number from UID chip */
-	if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) {
-		printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
-		setenv("serial#", "FAILED");
-	} else {
-		if (buf[0] != 0x70) {
-			/* Device Family Code */
-			printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
-			setenv("serial#", "FAILED");
-		}
-	}
-	/* Now check CRC */
-	tmp[0] = 0;
-	for (i = 0; i < 8; i++)
-		tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
-
-	if (tmp[0] != 0) {
-		printf("\nUID @ 0x%02x - BAD CRC!!!\n", CONFIG_SYS_UID_ADDR);
-		setenv("serial#", "FAILED");
-	} else {
-		/* CRC OK, set "serial" env variable */
-		sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
-			buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
-		setenv("serial#", (char *)&tmp[0]);
-	}
-
-	return(0);
-}
diff --git a/board/davinci/sffsdr/Kconfig b/board/davinci/sffsdr/Kconfig
deleted file mode 100644
index dc48f31..0000000
--- a/board/davinci/sffsdr/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_SFFSDR
-
-config SYS_BOARD
-	default "sffsdr"
-
-config SYS_VENDOR
-	default "davinci"
-
-config SYS_CONFIG_NAME
-	default "davinci_sffsdr"
-
-endif
diff --git a/board/davinci/sffsdr/MAINTAINERS b/board/davinci/sffsdr/MAINTAINERS
deleted file mode 100644
index 5c7e132..0000000
--- a/board/davinci/sffsdr/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SFFSDR BOARD
-#M:	-
-S:	Maintained
-F:	board/davinci/sffsdr/
-F:	include/configs/davinci_sffsdr.h
-F:	configs/davinci_sffsdr_defconfig
diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile
deleted file mode 100644
index 4ab30a4..0000000
--- a/board/davinci/sffsdr/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= sffsdr.o
-obj-y	+= board_init.o
diff --git a/board/davinci/sffsdr/board_init.S b/board/davinci/sffsdr/board_init.S
deleted file mode 100644
index ded0590..0000000
--- a/board/davinci/sffsdr/board_init.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-
-.globl	dv_board_init
-dv_board_init:
-
-	mov	pc, lr
diff --git a/board/davinci/sffsdr/config.mk b/board/davinci/sffsdr/config.mk
deleted file mode 100644
index 4fe9007..0000000
--- a/board/davinci/sffsdr/config.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# Copyright (C) 2008 Lyrtech <www.lyrtech.com>
-# Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
-#
-# Lyrtech SFF SDR board (ARM926EJS) cpu
-#
-# SFF SDR board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 87FF'FFFF
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0,
-# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc).
-#
-# we load ourself to 8400'0000 to provide at least 32MB spacing
-# between us and the Integrity kernel image
-CONFIG_SYS_TEXT_BASE = 0x84000000
diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c
deleted file mode 100644
index f6ab91e..0000000
--- a/board/davinci/sffsdr/sffsdr.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-#define DAVINCI_A3CR     (0x01E00014)	/* EMIF-A CS3 config register. */
-#define DAVINCI_A3CR_VAL (0x3FFFFFFD)	/* EMIF-A CS3 value for FPGA. */
-
-#define INTEGRITY_SYSCFG_OFFSET    0x7E8
-#define INTEGRITY_CHECKWORD_OFFSET 0x7F8
-#define INTEGRITY_CHECKWORD_VALUE  0x10ADBEEF
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	/* arch number of the board */
-	gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
-
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-	davinci_errata_workarounds();
-
-	/* Power on required peripherals */
-	lpsc_on(DAVINCI_LPSC_GPIO);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-	/* Powerup the DSP */
-	dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-	davinci_enable_uart0();
-	davinci_enable_emac();
-	davinci_enable_i2c();
-
-	lpsc_on(DAVINCI_LPSC_TIMER1);
-	timer_init();
-
-	return(0);
-}
-
-/* Read ethernet MAC address from Integrity data structure inside EEPROM.
- * Returns 1 if found, 0 otherwise.
- */
-static int sffsdr_read_mac_address(uint8_t *buf)
-{
-	u_int32_t value, mac[2], address;
-
-	/* Read Integrity data structure checkword. */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
-		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
-		goto err;
-	if (value != INTEGRITY_CHECKWORD_VALUE)
-		return 0;
-
-	/* Read SYSCFG structure offset. */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
-		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
-		goto err;
-	address = 0x800 + (int) value; /* Address of SYSCFG structure. */
-
-	/* Read NET CONFIG structure offset. */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
-		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
-		goto err;
-	address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
-	address += 12; /* Address of NET INTERFACE CONFIG structure. */
-
-	/* Read NET INTERFACE CONFIG 2 structure offset. */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
-		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
-		goto err;
-	address = 0x800 + 16 + (int) value;	/* Address of NET INTERFACE
-						 * CONFIG 2 structure. */
-
-	/* Read MAC address. */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
-		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
-		goto err;
-
-	buf[0] = mac[0] >> 24;
-	buf[1] = mac[0] >> 16;
-	buf[2] = mac[0] >> 8;
-	buf[3] = mac[0];
-	buf[4] = mac[1] >> 24;
-	buf[5] = mac[1] >> 16;
-
-	return 1; /* Found */
-
-err:
-	printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
-	return 0;
-}
-
-/* Platform dependent initialisation. */
-int misc_init_r(void)
-{
-	uint8_t i2cbuf;
-	uint8_t eeprom_enetaddr[6];
-
-	/* EMIF-A CS3 configuration for FPGA. */
-	REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
-
-	/* Configure I2C switch (PCA9543) to enable channel 0. */
-	i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
-	if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
-		      CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
-		printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR);
-		return 1;
-	}
-
-	/* Read Ethernet MAC address from EEPROM if available. */
-	if (sffsdr_read_mac_address(eeprom_enetaddr))
-		davinci_sync_env_enetaddr(eeprom_enetaddr);
-
-	return(0);
-}
diff --git a/board/davinci/sonata/Kconfig b/board/davinci/sonata/Kconfig
deleted file mode 100644
index 4440d95..0000000
--- a/board/davinci/sonata/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DAVINCI_SONATA
-
-config SYS_BOARD
-	default "sonata"
-
-config SYS_VENDOR
-	default "davinci"
-
-config SYS_CONFIG_NAME
-	default "davinci_sonata"
-
-endif
diff --git a/board/davinci/sonata/MAINTAINERS b/board/davinci/sonata/MAINTAINERS
deleted file mode 100644
index 40659e5..0000000
--- a/board/davinci/sonata/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SONATA BOARD
-#M:	-
-S:	Maintained
-F:	board/davinci/sonata/
-F:	include/configs/davinci_sonata.h
-F:	configs/davinci_sonata_defconfig
diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile
deleted file mode 100644
index 92e1a18..0000000
--- a/board/davinci/sonata/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= sonata.o
-obj-y	+= board_init.o
diff --git a/board/davinci/sonata/board_init.S b/board/davinci/sonata/board_init.S
deleted file mode 100644
index 0a47ad5..0000000
--- a/board/davinci/sonata/board_init.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Board-specific low level initialization code. Called at the very end
- * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
- * initialization required.
- *
- * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
- * Sonata boards, AFAIK, don't use this so it's just return by default. Ask
- * Visioneering if they reinvented the wheel once again to make sure :)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-
-.globl	dv_board_init
-dv_board_init:
-#ifdef SONATA_BOARD_GPIOWP
-	/* Set PINMUX0 to enable GPIO4 */
-	ldr	r0, _PINMUX0
-	ldr	r1, GPIO4_EN_MASK
-	ldr	r2, [r0]
-	and	r2, r2, r1
-	str	r2, [r0]
-
-	/* Enable GPIO LPSC module */
-	ldr	r0, PTSTAT
-
-gpio_ptstat_loop1:
-	ldr	r2, [r0]
-	tst	r2, $0x00000001
-	bne	gpio_ptstat_loop1
-
-	ldr	r1, MDCTL_GPIO
-	ldr	r2, [r1]
-	and	r2, r2, $0xfffffff8
-	orr	r2, r2, $0x00000003
-	str	r2, [r1]
-
-	orr	r2, r2, $0x00000200
-	str	r2, [r1]
-
-	ldr	r1, PTCMD
-	mov	r2, $0x00000001
-	str	r2, [r1]
-
-gpio_ptstat_loop2:
-	ldr	r2, [r0]
-	tst	r2, $0x00000001
-	bne	gpio_ptstat_loop2
-
-	ldr	r0, MDSTAT_GPIO
-gpio_mdstat_loop:
-	ldr	r2, [r0]
-	and	r2, r2, $0x0000001f
-	teq	r2, $0x00000003
-	bne	gpio_mdstat_loop
-
-	/* GPIO4 -> output */
-	ldr	r0, GPIO_DIR01
-	mov	r1, $0x10
-	ldr	r2, [r0]
-	bic	r2, r2, r0
-	str	r2, [r0]
-
-	/* Set it to 0 (Write Protect) */
-	ldr	r0, GPIO_CLR_DATA01
-	str	r1, [r0]
-#endif
-
-	mov	pc, lr
-
-#ifdef SONATA_BOARD_GPIOWP
-.ltorg
-
-GPIO4_EN_MASK:
-	.word	0xf77fffff
-MDCTL_GPIO:
-	.word	0x01c41a68
-MDSTAT_GPIO:
-	.word	0x01c41868
-GPIO_DIR01:
-	.word	0x01c67010
-GPIO_CLR_DATA01:
-	.word	0x01c6701c
-#endif
diff --git a/board/davinci/sonata/config.mk b/board/davinci/sonata/config.mk
deleted file mode 100644
index ed80707..0000000
--- a/board/davinci/sonata/config.mk
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Swaminathan <swami.iyer@ti.com>
-#
-# Davinci EVM board (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Davinci EVM has 1 bank of 256 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 9000'0000
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# Visioneering Corp. Sonata board (ARM926EJS) cpu
-#
-# Sonata board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
-#
-# Schmoogie board has 1 bank of 128 MB DDR RAM
-# Physical Address:
-# 8000'0000 to 8800'0000
-#
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-#
-# we load ourself to 8108 '0000
-#
-#
-
-#Provide at least 16MB spacing between us and the Linux Kernel image
-CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c
deleted file mode 100644
index f5c3258..0000000
--- a/board/davinci/sonata/sonata.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * SPDX-License-Identifier:	GPL-2.0+
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-	/* Configure AEMIF pins (although this should be configured at boot time
-	 * with pull-up/pull-down resistors) */
-	REG(PINMUX0) = 0x00000c1f;
-
-	davinci_errata_workarounds();
-
-	/* Power on required peripherals */
-	lpsc_on(DAVINCI_LPSC_GPIO);
-
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-	/* Powerup the DSP */
-	dsp_on();
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-	davinci_enable_uart0();
-	davinci_enable_emac();
-	davinci_enable_i2c();
-
-	lpsc_on(DAVINCI_LPSC_TIMER1);
-	timer_init();
-
-	return(0);
-}
-
-int misc_init_r(void)
-{
-	uint8_t eeprom_enetaddr[6];
-
-	/* Read Ethernet MAC address from EEPROM if available. */
-	if (dvevm_read_mac_address(eeprom_enetaddr))
-		davinci_sync_env_enetaddr(eeprom_enetaddr);
-
-	return(0);
-}
-
-#ifdef CONFIG_NAND_DAVINCI
-
-/* Set WP on deselect, write enable on select */
-static void nand_sonata_select_chip(struct mtd_info *mtd, int chip)
-{
-#define GPIO_SET_DATA01	0x01c67018
-#define GPIO_CLR_DATA01	0x01c6701c
-#define GPIO_NAND_WP	(1 << 4)
-#ifdef SONATA_BOARD_GPIOWP
-	if (chip < 0) {
-		REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
-	} else {
-		REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
-	}
-#endif
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
-	davinci_nand_init(nand);
-	nand->select_chip = nand_sonata_select_chip;
-	return 0;
-}
-
-#endif /* CONFIG_NAND_DAVINCI */
diff --git a/configs/cam_enc_4xx_defconfig b/configs/cam_enc_4xx_defconfig
deleted file mode 100644
index bf6b7f1..0000000
--- a/configs/cam_enc_4xx_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SPL=y
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_CAM_ENC_4XX=y
diff --git a/configs/davinci_dm355evm_defconfig b/configs/davinci_dm355evm_defconfig
deleted file mode 100644
index d3a03b2..0000000
--- a/configs/davinci_dm355evm_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM355EVM=y
diff --git a/configs/davinci_dm355leopard_defconfig b/configs/davinci_dm355leopard_defconfig
deleted file mode 100644
index 875c0b5..0000000
--- a/configs/davinci_dm355leopard_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM355LEOPARD=y
diff --git a/configs/davinci_dm365evm_defconfig b/configs/davinci_dm365evm_defconfig
deleted file mode 100644
index f841fd9..0000000
--- a/configs/davinci_dm365evm_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM365EVM=y
diff --git a/configs/davinci_dm6467Tevm_defconfig b/configs/davinci_dm6467Tevm_defconfig
deleted file mode 100644
index 4523d4a..0000000
--- a/configs/davinci_dm6467Tevm_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000"
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM6467EVM=y
diff --git a/configs/davinci_dm6467evm_defconfig b/configs/davinci_dm6467evm_defconfig
deleted file mode 100644
index 5208257..0000000
--- a/configs/davinci_dm6467evm_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="REFCLK_FREQ=27000000"
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DM6467EVM=y
diff --git a/configs/davinci_dvevm_defconfig b/configs/davinci_dvevm_defconfig
deleted file mode 100644
index 74e55b9..0000000
--- a/configs/davinci_dvevm_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_DVEVM=y
diff --git a/configs/davinci_schmoogie_defconfig b/configs/davinci_schmoogie_defconfig
deleted file mode 100644
index 64ed2c1..0000000
--- a/configs/davinci_schmoogie_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_SCHMOOGIE=y
diff --git a/configs/davinci_sffsdr_defconfig b/configs/davinci_sffsdr_defconfig
deleted file mode 100644
index 9eb0f07..0000000
--- a/configs/davinci_sffsdr_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_SFFSDR=y
diff --git a/configs/davinci_sonata_defconfig b/configs/davinci_sonata_defconfig
deleted file mode 100644
index d8f0f77..0000000
--- a/configs/davinci_sonata_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_TARGET_DAVINCI_SONATA=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index aa2b07b..95a2362 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,15 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+cam_enc_4xx      arm         arm926ejs      -           -           Heiko Schocher <hs@denx.de>
+dm355evm         arm         arm926ejs      -           -           Sandeep Paulraj <s-paulraj@ti.com>
+dm355leopard     arm         arm926ejs      -           -           Sandeep Paulraj <s-paulraj@ti.com>
+dm365evm         arm         arm926ejs      -           -           Sandeep Paulraj <s-paulraj@ti.com>
+dm6467evm        arm         arm926ejs      -           -           Sandeep Paulraj <s-paulraj@ti.com>
+dvevm            arm         arm926ejs      -           -
+schmoogie        arm         arm926ejs      -           -
+sffsdr           arm         arm926ejs      -           -
+sonata           arm         arm926ejs      -           -
 afeb9260         arm         arm926ejs      -           -           Sergey Lapin <slapin@ossfans.org>
 tny_a9260        arm         arm926ejs      -           -           Albin Tonnerre <albin.tonnerre@free-electrons.com>
 sbc35_a9g20      arm         arm926ejs      -           -           Albin Tonnerre <albin.tonnerre@free-electrons.com>
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index a397074..9bbe1b7 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -739,39 +739,6 @@ static int nand_davinci_dev_ready(struct mtd_info *mtd)
 
 static void nand_flash_init(void)
 {
-	/* This is for DM6446 EVM and *very* similar.  DO NOT GROW THIS!
-	 * Instead, have your board_init() set EMIF timings, based on its
-	 * knowledge of the clocks and what devices are hooked up ... and
-	 * don't even do that unless no UBL handled it.
-	 */
-#ifdef CONFIG_SOC_DM644X
-	u_int32_t	acfg1 = 0x3ffffffc;
-
-	/*------------------------------------------------------------------*
-	 *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
-	 *                                                                  *
-	 *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
-	 *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
-	 *                                                                  *
-	 *------------------------------------------------------------------*/
-	 acfg1 = 0
-		| (0 << 31)	/* selectStrobe */
-		| (0 << 30)	/* extWait */
-		| (1 << 26)	/* writeSetup	10 ns */
-		| (3 << 20)	/* writeStrobe	40 ns */
-		| (1 << 17)	/* writeHold	10 ns */
-		| (1 << 13)	/* readSetup	10 ns */
-		| (5 << 7)	/* readStrobe	60 ns */
-		| (1 << 4)	/* readHold	10 ns */
-		| (3 << 2)	/* turnAround	?? ns */
-		| (0 << 0)	/* asyncSize	8-bit bus */
-		;
-
-	__raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
-
-	/* NAND flash on CS2 */
-	__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
-#endif
 }
 
 void davinci_nand_init(struct nand_chip *nand)
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index f0ba8aa..d2c5817 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -328,9 +328,8 @@ static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
 		csr = readw(&musbr->txcsr);
 			
 		csr |= MUSB_CSR0_TXPKTRDY;
-#if !defined(CONFIG_SOC_DM365)
 		csr |= MUSB_CSR0_H_DIS_PING;
-#endif
+
 		writew(csr, &musbr->txcsr);
 		result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
 		if (result < 0)
@@ -353,9 +352,8 @@ static int ctrlreq_out_status_phase(struct usb_device *dev)
 	/* Set the StatusPkt bit */
 	csr = readw(&musbr->txcsr);
 	csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT);
-#if !defined(CONFIG_SOC_DM365)
 	csr |= MUSB_CSR0_H_DIS_PING;
-#endif
+
 	writew(csr, &musbr->txcsr);
 
 	/* Wait until TXPKTRDY bit is cleared */
@@ -373,9 +371,8 @@ static int ctrlreq_in_status_phase(struct usb_device *dev)
 
 	/* Set the StatusPkt bit and ReqPkt bit */
 	csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
-#if !defined(CONFIG_SOC_DM365)
 	csr |= MUSB_CSR0_H_DIS_PING;
-#endif
+
 	writew(csr, &musbr->txcsr);
 	result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
 
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
deleted file mode 100644
index f8785db..0000000
--- a/include/configs/cam_enc_4xx.h
+++ /dev/null
@@ -1,512 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
-#define CONFIG_SOC_DM365
-
-#define CONFIG_MACH_TYPE	MACH_TYPE_DAVINCI_DM365_EVM
-
-#define CONFIG_HOSTNAME			cam_enc_4xx
-
-#define	CONFIG_BOARD_LATE_INIT
-#define CONFIG_CAM_ENC_LED_MASK		0x0fc00000
-
-/* Memory Info */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x80000000
-#define PHYS_SDRAM_1_SIZE		(256 << 20)	/* 256 MiB */
-#define DDR_4BANKS				/* 4-bank DDR2 (256MB) */
-#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-
-/* Serial Driver info: UART0 for console  */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM1		0x01c20000
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			115200
-
-/* Network Configuration */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_EMAC_MDIO_PHY_NUM	0
-#define	CONFIG_SYS_EMAC_TI_CLKDIV	0xa9	/* 1MHz */
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT	10
-#define CONFIG_CMD_MII
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_RESET_PHY_R
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED		400000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE		0x10	/* SMBus host address */
-
-/* NAND: socketed, two chipselects, normally 2 GBytes */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS		2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
-/* socket has two chipselects, nCE0 gated by address BIT(14) */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-/* SPI support */
-#define CONFIG_SPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_DAVINCI_SPI
-#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
-#define CONFIG_SYS_SPI_CLK		davinci_clk_get(SPI_PLLDIV)
-#define CONFIG_SF_DEFAULT_SPEED		3000000
-#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_CMD_SF
-
-/* SD/MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
-#define CONFIG_MMC_MBLOCK
-
-/* U-Boot command configuration */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#endif
-
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CONFIG_SYS_PROMPT	"cam_enc_4xx> "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
-		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-
-#define CONFIG_MENU
-#define CONFIG_MENU_SHOW
-#define CONFIG_FIT
-#define CONFIG_BOARD_IMG_ADDR_R 0x80000000
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE			(16 << 10)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET		0x180000
-#define CONFIG_ENV_RANGE		0x040000
-#define CONFIG_ENV_OFFSET_REDUND	0x1c0000
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_CMD_ENV
-#define CONFIG_SYS_MMC_ENV_DEV	0
-#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
-#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
-#define CONFIG_ENV_IS_IN_MMC
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#define CONFIG_BOOTDELAY	3
-/*
- * 24MHz InputClock / 15 prediv -> 1.6 MHz timer running
- * Timeout 1 second.
- */
-#define CONFIG_AIT_TIMER_TIMEOUT	0x186a00
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-
-/* U-Boot memory configuration */
-#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START	0x80000000	/* physical address */
-#define CONFIG_SYS_MEMTEST_END		0x81000000	/* test 16MB RAM */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
-
-#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
-#define MTDPARTS_DEFAULT			\
-	"mtdparts="				\
-		"davinci_nand.0:"		\
-			"128k(spl),"		\
-			"384k(UBLheader),"	\
-			"1m(u-boot),"		\
-			"512k(env),"		\
-			"-(ubi)"
-
-#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
-#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
-
-/* Defines for SPL */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_POST_MEM_SUPPORT
-#define CONFIG_SPL_LDSCRIPT		"$(BOARDDIR)/u-boot-spl.lds"
-#define CONFIG_SPL_STACK		(0x00010000 + 0x7f00)
-
-#define CONFIG_SPL_TEXT_BASE		0x00000020 /*CONFIG_SYS_SRAM_START*/
-/* Provide at least 16MB spacing between us and the Linux Kernel image */
-#define CONFIG_SPL_PAD_TO		12320
-#define CONFIG_SPL_MAX_FOOTPRINT	12288
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_TEXT_BASE		0x81080000
-#endif
-
-#define CONFIG_SYS_NAND_BASE		0x02000000
-#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
-					CONFIG_SYS_NAND_PAGE_SIZE)
-
-#define CONFIG_SYS_NAND_ECCPOS		{				\
-				24, 25, 26, 27, 28,			\
-				29, 30, 31, 32, 33, 34, 35, 36, 37, 38,	\
-				39, 40, 41, 42, 43, 44, 45, 46, 47, 48,	\
-				49, 50, 51, 52, 53, 54, 55, 56, 57, 58,	\
-				59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
-#define CONFIG_SYS_NAND_ECCSIZE		0x200
-#define CONFIG_SYS_NAND_ECCBYTES	10
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-#define CONFIG_SYS_NAND_MAX_ECCPOS	56
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-
-/*
- * RBL searches from Block n (n = 1..24)
- * so we can define, how many UBL Headers
- * we can write before the real spl code
- */
-#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
-
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x81080000 /* u-boot TEXT_BASE */
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
-
-/*
- * Post tests for memory testing
- */
-#define CONFIG_POST	CONFIG_SYS_POST_MEMORY
-#define _POST_WORD_ADDR	0x0
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0xa0000
-#define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE	0x100000
-
-/* for UBL header */
-#define CONFIG_SYS_UBL_BLOCK		(CONFIG_SYS_NAND_PAGE_SIZE)
-
-#define CONFIG_SYS_DM36x_PLL1_PLLM	0x55
-#define CONFIG_SYS_DM36x_PLL1_PREDIV	0x8005
-#define CONFIG_SYS_DM36x_PLL2_PLLM	0x09
-#define CONFIG_SYS_DM36x_PLL2_PREDIV	0x8000
-#define CONFIG_SYS_DM36x_PERI_CLK_CTRL	0x243F04FC
-#define CONFIG_SYS_DM36x_PLL1_PLLDIV1	0x801b
-#define CONFIG_SYS_DM36x_PLL1_PLLDIV2	0x8001
-/* POST DIV 680/2 = 340Mhz  -> MJCP and HDVICP bus interface clock */
-#define CONFIG_SYS_DM36x_PLL1_PLLDIV3	0x8001
-/*
- * POST DIV 680/4 = 170Mhz  -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
- * interface clk)
- */
-#define CONFIG_SYS_DM36x_PLL1_PLLDIV4	0x8003
-/* POST DIV 680/2 = 340Mhz  -> VPSS */
-#define CONFIG_SYS_DM36x_PLL1_PLLDIV5	0x8001
-/* POST DIV 680/9 = 75.6 Mhz -> VENC */
-#define CONFIG_SYS_DM36x_PLL1_PLLDIV6	0x8008
-/*
- * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
- * down to 340 Mhz)
- */
-#define CONFIG_SYS_DM36x_PLL1_PLLDIV7	0x8000
-/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
-#define CONFIG_SYS_DM36x_PLL1_PLLDIV8	0x8006
-/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
-#define CONFIG_SYS_DM36x_PLL1_PLLDIV9	0x801b
-
-#define CONFIG_SYS_DM36x_PLL2_PLLDIV1	0x8011
-/* POST DIV 432/1=432 Mhz  -> ARM926/(HDVICP block) clk */
-#define CONFIG_SYS_DM36x_PLL2_PLLDIV2	0x8000
-#define CONFIG_SYS_DM36x_PLL2_PLLDIV3	0x8001
-/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
-#define CONFIG_SYS_DM36x_PLL2_PLLDIV4	0x8014
-/* POST DIV 432/16=27 Mhz  -> VENC(For SD modes, requires) */
-#define CONFIG_SYS_DM36x_PLL2_PLLDIV5	0x800f
-
-/*
- * READ LATENCY 7 (CL + 2)
- * CONFIG_PWRDNEN = 1
- * CONFIG_EXT_STRBEN = 1
- */
-#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR	(0 \
-	| DV_DDR_PHY_EXT_STRBEN \
-	| DV_DDR_PHY_PWRDNEN \
-	| (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-
-/*
- * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
- * T_RP  = (trp/DDR_CLK) - 1  = (12.5 / 2.941) - 1
- * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
- * T_WR  = (twr/DDR_CLK) - 1  = (15 / 2.941) - 1
- * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
- * T_RC  = (trc/DDR_CLK) - 1  = (57.5 / 2.941) - 1
- * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
- * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
- */
-#define CONFIG_SYS_DM36x_DDR2_SDTIMR	(0 \
-	| (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
-	| (4  << DV_DDR_SDTMR1_RP_SHIFT) \
-	| (4  << DV_DDR_SDTMR1_RCD_SHIFT) \
-	| (5  << DV_DDR_SDTMR1_WR_SHIFT) \
-	| (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
-	| (19 << DV_DDR_SDTMR1_RC_SHIFT) \
-	| (2  << DV_DDR_SDTMR1_RRD_SHIFT) \
-	| (2  << DV_DDR_SDTMR1_WTR_SHIFT))
-
-/*
- * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
- * T_XP  = tCKE - 1 = 3 - 2
- * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
- * T_XSRD = txsrd - 1 = 200 - 1
- * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
- * T_CKE = tcke - 1     = 3 - 1
- */
-#define CONFIG_SYS_DM36x_DDR2_SDTIMR2	(0 \
-	| (8  << DV_DDR_SDTMR2_RASMAX_SHIFT) \
-	| (2  << DV_DDR_SDTMR2_XP_SHIFT) \
-	| (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
-	| (199 <<  DV_DDR_SDTMR2_XSRD_SHIFT) \
-	| (2 <<  DV_DDR_SDTMR2_RTP_SHIFT) \
-	| (2 <<  DV_DDR_SDTMR2_CKE_SHIFT))
-
-/* PR_OLD_COUNT = 0xfe */
-#define CONFIG_SYS_DM36x_DDR2_PBBPR	0x000000FE
-/* refresh rate = 0x768 */
-#define CONFIG_SYS_DM36x_DDR2_SDRCR	0x00000768
-
-#define CONFIG_SYS_DM36x_DDR2_SDBCR	(0 \
-	| (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
-	| (3 << DV_DDR_SDCR_IBANK_SHIFT) \
-	| (5 << DV_DDR_SDCR_CL_SHIFT) \
-	| (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	\
-	| (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
-	| (1 << DV_DDR_SDCR_DDREN_SHIFT) \
-	| (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT)	\
-	| (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
-	| (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
-	| (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
-
-#define CONFIG_SYS_DM36x_AWCCR	0xff
-#define CONFIG_SYS_DM36x_AB1CR	0x40400204
-#define CONFIG_SYS_DM36x_AB2CR	0x04ca2650
-
-/* All Video Inputs */
-#define CONFIG_SYS_DM36x_PINMUX0	0x00000000
-/*
- * All Video Outputs,
- * GPIO 86, 87 + 90 0x0000f030
- */
-#define CONFIG_SYS_DM36x_PINMUX1	0x00530002
-#define CONFIG_SYS_DM36x_PINMUX2	0x00001815
-/*
- * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
- * GPIO 25 0x60000000
- */
-#define CONFIG_SYS_DM36x_PINMUX3	0x9b5affff
-/*
- * MMC/SD0 instead of MS, SPI0
- * GPIO 34 0x0000c000
- */
-#define CONFIG_SYS_DM36x_PINMUX4	0x00002655
-
-/*
- * Default environment settings
- */
-
-#define DVN4XX_UBOOT_ADDR_R_RAM		0x80000000
-/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
-#define DVN4XX_UBOOT_ADDR_R_NAND_SPL	0x80000800
-/*
- * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
- * CONFIG_SYS_NAND_PAGE_SIZE))
- */
-#define DVN4XX_UBOOT_ADDR_R_UBOOT	0x80003800
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u_boot_addr_r=" __stringify(DVN4XX_UBOOT_ADDR_R_RAM) "\0"	\
-	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.ubl\0"		\
-	"load=tftp ${u_boot_addr_r} ${u-boot}\0"			\
-	"pagesz=" __stringify(CONFIG_SYS_NAND_PAGE_SIZE) "\0"		\
-	"writeheader=nandrbl rbl;nand erase 20000 ${pagesz};"		\
-		"nand write ${u_boot_addr_r} 20000 ${pagesz};"		\
-		"nandrbl uboot\0"					\
-	"writenand_spl=nandrbl rbl;nand erase 0 3000;"			\
-		"nand write " __stringify(DVN4XX_UBOOT_ADDR_R_NAND_SPL)	\
-		" 0 3000;nandrbl uboot\0"				\
-	"writeuboot=nandrbl uboot;"					\
-		"nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
-		 __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE)		\
-		";nand write " __stringify(DVN4XX_UBOOT_ADDR_R_UBOOT)	\
-		" " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "	\
-		__stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"		\
-	"update=run load writenand_spl writeuboot\0"			\
-	"bootcmd=run net_nfs\0"						\
-	"rootpath=/opt/eldk-arm/arm\0"					\
-	"mtdids=" MTDIDS_DEFAULT "\0"					\
-	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
-	"netdev=eth0\0"							\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0"	\
-	"addcon=setenv bootargs ${bootargs} console=ttyS0,"		\
-		"${baudrate}n8\0"					\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0"	\
-	"rootpath=/opt/eldk-arm/arm\0"					\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0"		\
-	"kernel_addr_r=80600000\0"					\
-	"load_kernel=tftp ${kernel_addr_r} ${bootfile}\0"		\
-	"ubi_load_kernel=ubi part ubi 2048;ubifsmount ubi:${img_volume};" \
-		"ubifsload ${kernel_addr_r} boot/uImage\0"		\
-	"fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0"		\
-	"img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0"		\
-	"img_file=" __stringify(CONFIG_HOSTNAME) "/ait.itb\0"		\
-	"header_addr=20000\0"						\
-	"img_writeheader=nandrbl rbl;"					\
-		"nand erase ${header_addr} ${pagesz};"			\
-		"nand write ${img_addr_r} ${header_addr} ${pagesz};"	\
-		"nandrbl uboot\0"					\
-	"img_writespl=nandrbl rbl;nand erase 0 3000;"			\
-		"nand write ${img_addr_r} 0 3000;nandrbl uboot\0"	\
-	"img_writeuboot=nandrbl uboot;"					\
-		"nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
-		 __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE)		\
-		";nand write ${img_addr_r} "				\
-		__stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "		\
-		__stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"		\
-	"img_writedfenv=ubi part ubi 2048;"				\
-		"ubi write ${img_addr_r} default ${filesize}\0"		\
-	"img_volume=rootfs1\0"						\
-	"img_writeramdisk=ubi part ubi 2048;"				\
-		"ubi write ${img_addr_r} ${img_volume} ${filesize}\0"	\
-	"load_img=tftp ${fit_addr_r} ${img_file}\0"			\
-	"net_nfs=run load_kernel; "					\
-		"run nfsargs addip addcon addmtd addmisc;"		\
-		"bootm ${kernel_addr_r}\0"				\
-	"ubi_ubi=run ubi_load_kernel; "					\
-		"run ubiargs addip addcon addmtd addmisc;"		\
-		"bootm ${kernel_addr_r}\0"				\
-	"ubiargs=setenv bootargs ubi.mtd=4,2048"			\
-		" root=ubi0:${img_volume} rw rootfstype=ubifs\0"	\
-	"app_reset=no\0"						\
-	"dvn_app_vers=void\0"						\
-	"dvn_boot_vers=void\0"						\
-	"savenewvers=run savetmpparms restoreparms; saveenv;"		\
-		"run restoretmpparms\0"					\
-	"savetmpparms=setenv y_ipaddr ${ipaddr};"			\
-		"setenv y_netmask ${netmask};"				\
-		"setenv y_serverip ${serverip};"			\
-		"setenv y_gatewayip ${gatewayip}\0"			\
-	"saveparms=setenv x_ipaddr ${ipaddr};"				\
-		"setenv x_netmask ${netmask};"				\
-		"setenv x_serverip ${serverip};"			\
-		"setenv x_gatewayip ${gatewayip}\0"			\
-	"restoreparms=setenv ipaddr ${x_ipaddr};"			\
-		"setenv netmask ${x_netmask};"				\
-		"setenv serverip ${x_serverip};"			\
-		"setenv gatewayip ${x_gatewayip}\0"			\
-	"restoretmpparms=setenv ipaddr ${y_ipaddr};"			\
-		"setenv netmask ${y_netmask};"				\
-		"setenv serverip ${y_serverip};"			\
-		"setenv gatewayip ${y_gatewayip}\0"			\
-	"\0"
-
-/* USB Configuration */
-#define CONFIG_USB_DAVINCI
-#define CONFIG_MUSB_HCD
-#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
-				USBPHY_PHY24MHZ)
-
-#define CONFIG_CMD_USB         /* include support for usb cmd */
-#define CONFIG_USB_STORAGE     /* MSC class support */
-#define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
-#define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
-#define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
-
-#undef DAVINCI_DM365EVM
-#define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
-#define PINMUX4_USBDRVBUS_BITSET         0x2000
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
deleted file mode 100644
index 16b901b..0000000
--- a/include/configs/davinci_dm355evm.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Spectrum Digital TMS320DM355 EVM board */
-#define DAVINCI_DM355EVM
-
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
-#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
-#define CONFIG_SOC_DM355
-
-/* Memory Info */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x80000000
-#define PHYS_SDRAM_1_SIZE		(128 << 20)	/* 128 MiB */
-
-/* Serial Driver info: UART0 for console  */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM1		0x01c20000
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			115200
-
-/* Ethernet:  external DM9000 */
-#define CONFIG_DRIVER_DM9000		1
-#define CONFIG_DM9000_BASE		0x04014000
-#define DM9000_IO			CONFIG_DM9000_BASE
-#define DM9000_DATA			(CONFIG_DM9000_BASE + 2)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED		400000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE		0x10	/* SMBus host address */
-
-/* NAND: socketed, two chipselects, normally 2 GBytes */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS		2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
-/* socket has two chipselects, nCE0 gated by address BIT(14) */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_MAX_CHIPS	2
-
-/* SD/MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
-#define CONFIG_DAVINCI_MMC_SD1
-#define CONFIG_MMC_MBLOCK
-
-/* USB: OTG connector */
-/* NYET -- #define CONFIG_USB_DAVINCI */
-
-/* U-Boot command configuration */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#endif
-
-#ifdef CONFIG_USB_DAVINCI
-#define CONFIG_MUSB_HCD
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#else
-#undef CONFIG_MUSB_HCD
-#undef CONFIG_CMD_USB
-#undef CONFIG_USB_STORAGE
-#endif
-
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CONFIG_SYS_PROMPT	"DM355 EVM # "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
-		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE		(256 << 10)	/* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET	0x3C0000
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_CMD_ENV
-#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
-#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
-#define CONFIG_ENV_IS_IN_MMC
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_BOOTCOMMAND \
-		"dhcp;bootm"
-#define CONFIG_BOOTARGS \
-		"console=ttyS0,115200n8 " \
-		"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* U-Boot memory configuration */
-#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
-#define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
-
-
-/* NAND configuration ... socketed with two chipselects.  It normally comes
- * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other
- * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC.  (MLC
- * pretty much demands the 4-bit ECC support.)  You can of course swap in
- * other parts, including small page ones.
- *
- * This presents a single read-only partition for all bootloader stuff.
- * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and
- * some extra space to help cope with bad blocks in that data.  Linux
- * shouldn't care about its detailed layout, and will probably want to use
- * UBI/UBFS for the rest (except maybe on smallpage chips).  It's easy to
- * override this default partitioning using MTDPARTS and cmdlinepart.
- */
-#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-/*  Use same layout for 128K/256K blocks; allow some bad blocks */
-#define PART_BOOT		"2m(bootloader)ro,"
-#else
-/* Assume 16K erase blocks; allow a few bad ones. */
-#define PART_BOOT		"512k(bootloader)ro,"
-#endif
-
-#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
-#define PART_REST		"-(filesystem)"
-
-#define MTDPARTS_DEFAULT	\
-	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
-
-#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR		\
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
deleted file mode 100644
index 4eed722..0000000
--- a/include/configs/davinci_dm355leopard.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define DAVINCI_DM355LEOPARD
-
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
-#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
-#define CONFIG_SOC_DM355				/* DM355 based board */
-
-/* Memory Info */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x80000000
-#define PHYS_SDRAM_1_SIZE		(128 << 20)	/* 128 MiB */
-
-/* Serial Driver info: UART0 for console  */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM1		0x01c20000
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			115200
-
-/* Ethernet:  external DM9000 */
-#define CONFIG_DRIVER_DM9000		1
-#define CONFIG_DM9000_BASE		0x04000000
-#define DM9000_IO			CONFIG_DM9000_BASE
-#define DM9000_DATA			(CONFIG_DM9000_BASE + 16)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED		400000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE		0x10
-
-/* NAND */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS		2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_HW_ECC
-
-#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-
-/* U-Boot command configuration */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#endif
-
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CONFIG_SYS_PROMPT	"DM355 LEOPARD # "
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
-		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE		(256 << 10)	/* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET	0x3C0000
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OVERWRITE
-#endif
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTCOMMAND	"dhcp;bootm"
-#define CONFIG_BOOTARGS		\
-			"console=ttyS0,115200n8 " \
-			"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* U-Boot memory configuration */
-#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
-#define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
-
-#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-#define PART_BOOT		"2m(bootloader)ro,"
-#else
-/* Assume 16K erase blocks; allow a few bad ones. */
-#define PART_BOOT		"512k(bootloader)ro,"
-#endif
-
-#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
-#define PART_REST		"-(filesystem)"
-
-#define MTDPARTS_DEFAULT	\
-	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
-
-#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR		\
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
deleted file mode 100644
index c50c059..0000000
--- a/include/configs/davinci_dm365evm.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Spectrum Digital TMS320DM365 EVM board */
-#define DAVINCI_DM365EVM
-
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
-#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
-#define CONFIG_SOC_DM365
-
-/* Memory Info */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x80000000
-#define PHYS_SDRAM_1_SIZE		(128 << 20)	/* 128 MiB */
-
-/* Serial Driver info: UART0 for console  */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM1		0x01c20000
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			115200
-
-/* EEPROM definitions for EEPROM on DM365 EVM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
-
-/* Network Configuration */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT	10
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED		400000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE		0x10	/* SMBus host address */
-
-/* NAND: socketed, two chipselects, normally 2 GBytes */
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS		2
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define CONFIG_SYS_NAND_PAGE_2K
-
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
-/* socket has two chipselects, nCE0 gated by address BIT(14) */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_MAX_CHIPS	2
-
-/* SD/MMC */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DAVINCI_MMC
-#define CONFIG_DAVINCI_MMC_SD1
-#define CONFIG_MMC_MBLOCK
-
-#define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
-#define PINMUX4_USBDRVBUS_BITSET         0x2000
-
-/* USB Configuration */
-#define CONFIG_USB_DAVINCI
-#define CONFIG_MUSB_HCD
-
-#ifdef CONFIG_USB_DAVINCI
-#define CONFIG_CMD_USB         /* include support for usb      */
-#define CONFIG_CMD_STORAGE     /* include support for usb      */
-#define CONFIG_CMD_FAT         /* include support for FAT/storage*/
-#define CONFIG_DOS_PARTITION   /* include support for FAT/storage*/
-#endif
-
-#ifdef CONFIG_MUSB_HCD         /* include support for usb host */
-#define CONFIG_CMD_USB         /* include support for usb cmd */
-#define CONFIG_USB_STORAGE     /* MSC class support */
-#define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
-#define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
-#define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
-
-#ifdef CONFIG_USB_KEYBOARD     /* HID class support */
-#define CONFIG_SYS_USB_EVENT_POLL
-
-#define CONFIG_PREBOOT "usb start"
-#endif /* CONFIG_USB_KEYBOARD */
-#endif /* CONFIG_MUSB_HCD */
-
-#ifdef CONFIG_MUSB_UDC
-#define CONFIG_USB_DEVICE              1
-#define CONFIG_USB_TTY                 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV   1
-#define CONFIG_USBD_VENDORID           0x0451
-#define CONFIG_USBD_PRODUCTID          0x5678
-#define CONFIG_USBD_MANUFACTURER       "Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME       "DM365VM"
-#endif /* CONFIG_MUSB_UDC */
-
-/* U-Boot command configuration */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#ifdef CONFIG_MMC
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_MMC
-#endif
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
-#endif
-
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CONFIG_SYS_PROMPT	"DM36x EVM # "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
-		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP
-
-#ifdef CONFIG_NAND_DAVINCI
-#define CONFIG_ENV_SIZE		(256 << 10)	/* 256 KiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET	0x3C0000
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_CMD_ENV
-#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
-#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
-#define CONFIG_ENV_IS_IN_MMC
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTCOMMAND \
-		"dhcp;bootm"
-#define CONFIG_BOOTARGS \
-		"console=ttyS0,115200n8 " \
-		"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_TIMESTAMP
-
-/* U-Boot memory configuration */
-#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
-#define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
-
-
-/* NAND configuration issocketed with two chipselects just like the DM355 EVM.
- * It normally comes with a 2GByte SLC part with 2KB pages
- * (and 128KB erase blocks); other
- * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC.  (MLC
- * pretty much demands the 4-bit ECC support.)  You can of course swap in
- * other parts, including small page ones.
- */
-#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
-
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-/*  Use same layout for 128K/256K blocks; allow some bad blocks */
-#define PART_BOOT		"2m(bootloader)ro,"
-#else
-/* Assume 16K erase blocks; allow a few bad ones. */
-#define PART_BOOT		"512k(bootloader)ro,"
-#endif
-
-#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
-#define PART_REST		"-(filesystem)"
-
-#define MTDPARTS_DEFAULT	\
-	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
-
-#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR		\
-	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
deleted file mode 100644
index 2c5a837..0000000
--- a/include/configs/davinci_dm6467evm.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Spectrum Digital TMS320DM6467 EVM board */
-#define DAVINCI_DM6467EVM
-#define CONFIG_SYS_USE_NAND
-#define CONFIG_SYS_NAND_SMALLPAGE
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-/* SoC Configuration */
-
-/* Clock rates detection */
-#ifndef __ASSEMBLY__
-extern unsigned int davinci_arm_clk_get(void);
-#endif
-
-/* Arm Clock frequency    */
-#define CONFIG_SYS_CLK_FREQ	davinci_arm_clk_get()
-/* Timer Input clock freq */
-#define CONFIG_SYS_HZ_CLOCK		(CONFIG_SYS_CLK_FREQ/2)
-#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SOC_DM646X
-
-/* EEPROM definitions for EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
-
-/* Memory Info */
-#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
-#define CONFIG_SYS_MEMTEST_START	0x80000000
-#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1			0x80000000	/* DDR Start */
-#define PHYS_SDRAM_1_SIZE		(256 << 20)	/* DDR size 256MB */
-
-/* Linux interfacing */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_SYS_BARGSIZE		1024		/* Bootarg Size */
-#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* kernel address */
-#define CONFIG_REVISION_TAG
-
-/* Serial Driver info */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	4
-#define CONFIG_SYS_NS16550_COM1		0x01c20000
-#define CONFIG_SYS_NS16550_CLK		24000000
-#define CONFIG_CONS_INDEX		1
-#define CONFIG_BAUDRATE			115200
-
-/* I2C Configuration */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED		80000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE		10
-
-/* Network & Ethernet Configuration */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT	10
-#define CONFIG_CMD_NET
-
-/* Flash & Environment */
-#define CONFIG_SYS_NO_FLASH
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_MASK_CLE	0x80000
-#define CONFIG_SYS_NAND_MASK_ALE	0x40000
-#define CONFIG_SYS_NAND_CS		2
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KiB */
-#define CONFIG_SYS_NAND_BASE_LIST	{0x42000000, }
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_ENV_OFFSET		0
-#else
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE			(4 << 10)	/* 4 KiB */
-#endif
-
-/* U-Boot general configuration */
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CONFIG_SYS_PROMPT	"DM6467 EVM > "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE		\
-			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_BOOTCOMMAND		"source 0x82080000; dhcp; bootm"
-#define CONFIG_BOOTARGS			\
-					"mem=120M console=ttyS0,115200n8 " \
-					"root=/dev/hda1 rw noinitrd ip=dhcp"
-
-/* U-Boot commands */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#ifdef CONFIG_SYS_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#define CONFIG_CMD_NAND
-#endif
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
deleted file mode 100644
index 2467f70..0000000
--- a/include/configs/davinci_dvevm.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Define this to make U-Boot skip low level initialization when loaded
- * by initial bootloader. Not required by NAND U-Boot version but IS
- * required for a NOR version used to burn the real NOR U-Boot into
- * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
- * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
- * NOR U-Boot is loaded directly from Flash so it must perform all the
- * low level initialization itself. NAND version is loaded by an initial
- * bootloader (UBL in TI-ese) that performs such an initialization so it's
- * skipped in NAND version. The third DaVinci boot mode loads a bootloader
- * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
- * performing low level init prior to loading. All that means we can NOT use
- * NAND version to put U-Boot into NOR because it doesn't have NOR support and
- * we can NOT use NOR version because it performs low level initialization
- * effectively destroying itself in DDR memory. That's why a separate NOR
- * version with this define is needed. It is loaded via UART, then one uses
- * it to somehow download a proper NOR version built WITHOUT this define to
- * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
- * NOR support into the initial bootloader so it won't be needed but DaVinci
- * static RAM might be too small for this (I have something like 2Kbytes left
- * as of now, without NOR support) so this might've not happened...
- *
-#define CONFIG_NOR_UART_BOOT
- */
-
-/*=======*/
-/* Board */
-/*=======*/
-#define DV_EVM
-#define CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_SYS_USE_NAND
-/*===================*/
-/* SoC Configuration */
-/*===================*/
-#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/*====================================================*/
-/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
-/* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
-/*====================================================*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
-/*=============*/
-/* Memory Info */
-/*=============*/
-#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
-#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
-#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
-#define PHYS_SDRAM_1_SIZE	0x10000000	/* DDR size 256MB */
-
-#define DDR_8BANKS				/* 8-bank DDR2 (256MB) */
-/*====================*/
-/* Serial Driver info */
-/*====================*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
-#define CONFIG_BAUDRATE		115200		/* Default baud rate */
-/*===================*/
-/* I2C Configuration */
-/*===================*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10	/* Bogus, master-only in U-Boot */
-/*==================================*/
-/* Network & Ethernet Configuration */
-/*==================================*/
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT	10
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS		2
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
-#ifdef CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_ENV_SECT_SIZE	512	/* Env sector Size */
-#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		\
-	"nand0=davinci_nand.0"
-#define MTDPARTS_DEFAULT	\
-	"mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)"
-#else
-#define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
-#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
-#endif
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE		0x02000000
-#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
-#elif defined(CONFIG_SYS_USE_NOR)
-#ifdef CONFIG_NOR_UART_BOOT
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#else
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of flash banks */
-#define CONFIG_SYS_FLASH_SECT_SZ	0x10000		/* 64KB sect size AMD Flash */
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ*3)
-#define PHYS_FLASH_1		0x02000000	/* CS2 Base address	 */
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB	 */
-#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
-#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_FLASH_SECT_SZ	/* Env sector Size */
-#endif
-/*==============================*/
-/* U-Boot general configuration */
-/*==============================*/
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer sz */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-#define CONFIG_MUSB_HCD
-#define CONFIG_USB_DAVINCI
-/*===================*/
-/* Linux Information */
-/*===================*/
-#define LINUX_BOOT_PARAM_ADDR	0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS		"mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTCOMMAND	"setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000"
-/*=================*/
-/* U-Boot commands */
-/*=================*/
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_BDI
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#ifdef CONFIG_SYS_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#define CONFIG_CMD_NAND
-#elif defined(CONFIG_SYS_USE_NOR)
-#define CONFIG_CMD_JFFS2
-#else
-#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
-#endif
-/*==========================*/
-/* USB MSC support (if any) */
-/*==========================*/
-#ifdef CONFIG_USB_DAVINCI
-#define CONFIG_CMD_USB
-#ifdef CONFIG_MUSB_HCD
-#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_STORAGE
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-#ifdef CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_PREBOOT "usb start"
-#endif
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
deleted file mode 100644
index 2505465..0000000
--- a/include/configs/davinci_schmoogie.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*=======*/
-/* Board */
-/*=======*/
-#define SCHMOOGIE
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_USE_NAND
-#define MACH_TYPE_SCHMOOGIE 1255
-#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
-
-/*===================*/
-/* SoC Configuration */
-/*===================*/
-#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/*=============*/
-/* Memory Info */
-/*=============*/
-#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
-#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
-#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
-#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
-#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
-/*====================*/
-/* Serial Driver info */
-/*====================*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
-#define CONFIG_BAUDRATE		115200		/* Default baud rate */
-/*===================*/
-/* I2C Configuration */
-/*===================*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10    /* Bogus, master-only in U-Boot */
-/*==================================*/
-/* Network & Ethernet Configuration */
-/*==================================*/
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT	10
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS		2
-#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
-#define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
-#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE		0x02000000
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
-/*=====================*/
-/* Board related stuff */
-/*=====================*/
-#define CONFIG_RTC_DS1307		/* RTC chip on SCHMOOGIE */
-#define CONFIG_SYS_I2C_RTC_ADDR	0x6f	/* RTC chip I2C address */
-#define CONFIG_UID_DS28CM00		/* Unique ID on SCHMOOGIE */
-#define CONFIG_SYS_UID_ADDR		0x50	/* UID chip I2C address */
-/*==============================*/
-/* U-Boot general configuration */
-/*==============================*/
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer sz */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-/*===================*/
-/* Linux Information */
-/*===================*/
-#define LINUX_BOOT_PARAM_ADDR	0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS		"mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTCOMMAND	"setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
-/*=================*/
-/* U-Boot commands */
-/*=================*/
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NAND
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
deleted file mode 100644
index e773835..0000000
--- a/include/configs/davinci_sffsdr.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* Board */
-#define SFFSDR
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_SYS_USE_NAND
-#define CONFIG_SYS_USE_DSPLINK		/* don't power up the DSP. */
-/* SoC Configuration */
-#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
-/* Memory Info */
-#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
-#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
-#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
-#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
-#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
-/* Serial Driver info */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
-#define CONFIG_BAUDRATE		115200		/* Default baud rate */
-/* I2C Configuration */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10    /* Bogus, master-only in U-Boot */
-/* Network & Ethernet Configuration */
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT	10
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-/* Flash & Environment */
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS		2
-#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
-#define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
-#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE		0x02000000
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
-/* I2C switch definitions for PCA9543 chip */
-#define CONFIG_SYS_I2C_PCA9543_ADDR		0x70
-#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN	0	/* Single register. */
-#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0	0x01	/* Enable channel 0. */
-/* U-Boot general configuration */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds. */
-#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE							\
-		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print buffer size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* Default Linux kernel
-						 * load address. */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far,
-					 * may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-/* Linux Information */
-#define LINUX_BOOT_PARAM_ADDR	0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS			\
-	"mem=56M "			\
-	"console=ttyS0,115200n8 "	\
-	"root=/dev/nfs rw noinitrd ip=dhcp "	\
-	"nfsroot=${serverip}:/nfsroot/sffsdr "	\
-	"eth0=${ethaddr}"
-#define CONFIG_BOOTCOMMAND	\
-	"nand read 87A00000 100000 300000;"	\
-	"bootelf 87A00000"
-/* U-Boot commands */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF	/* Needed to load Integrity kernel. */
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
deleted file mode 100644
index dae37cd..0000000
--- a/include/configs/davinci_sonata.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Define this to make U-Boot skip low level initialization when loaded
- * by initial bootloader. Not required by NAND U-Boot version but IS
- * required for a NOR version used to burn the real NOR U-Boot into
- * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
- * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
- * NOR U-Boot is loaded directly from Flash so it must perform all the
- * low level initialization itself. NAND version is loaded by an initial
- * bootloader (UBL in TI-ese) that performs such an initialization so it's
- * skipped in NAND version. The third DaVinci boot mode loads a bootloader
- * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
- * performing low level init prior to loading. All that means we can NOT use
- * NAND version to put U-Boot into NOR because it doesn't have NOR support and
- * we can NOT use NOR version because it performs low level initialization
- * effectively destroying itself in DDR memory. That's why a separate NOR
- * version with this define is needed. It is loaded via UART, then one uses
- * it to somehow download a proper NOR version built WITHOUT this define to
- * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
- * NOR support into the initial bootloader so it won't be needed but DaVinci
- * static RAM might be too small for this (I have something like 2Kbytes left
- * as of now, without NOR support) so this might've not happened...
- *
-#define CONFIG_NOR_UART_BOOT
- */
-
-/*=======*/
-/* Board */
-/*=======*/
-#define SONATA_BOARD
-#define CONFIG_SYS_NAND_SMALLPAGE
-#define CONFIG_SYS_USE_NOR
-#define MACH_TYPE_SONATA 1254
-#define CONFIG_MACH_TYPE MACH_TYPE_SONATA
-/*===================*/
-/* SoC Configuration */
-/*===================*/
-#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
-#define CONFIG_SOC_DM644X
-/*====================================================*/
-/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
-/* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
-/*====================================================*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
-/*=============*/
-/* Memory Info */
-/*=============*/
-#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
-#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
-#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
-#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
-#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
-/*====================*/
-/* Serial Driver info */
-/*====================*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
-#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
-#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
-#define CONFIG_BAUDRATE		115200		/* Default baud rate */
-/*===================*/
-/* I2C Configuration */
-/*===================*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_DAVINCI
-#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10    /* Bogus, master-only in U-Boot */
-/*==================================*/
-/* Network & Ethernet Configuration */
-/*==================================*/
-#define CONFIG_DRIVER_TI_EMAC
-#define CONFIG_MII
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT	10
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#ifdef CONFIG_SYS_USE_NAND
-#define CONFIG_NAND_DAVINCI
-#define CONFIG_SYS_NAND_CS		2
-#undef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_OVERWRITE		/* instead if obsoleted forceenv() */
-#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
-#define CONFIG_ENV_SECT_SIZE	512	/* Env sector Size */
-#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#define CONFIG_SYS_NAND_BASE		0x02000000
-#define CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
-#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
-#elif defined(CONFIG_SYS_USE_NOR)
-#ifdef CONFIG_NOR_UART_BOOT
-#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
-#else
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-#define CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of flash banks */
-#define CONFIG_SYS_FLASH_SECT_SZ	0x20000		/* 128KB sect size AMD Flash */
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ*2)
-#define CONFIG_ENV_SIZE		CONFIG_SYS_FLASH_SECT_SZ
-#define PHYS_FLASH_1		0x02000000	/* CS2 Base address	 */
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
-#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB	 */
-#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
-#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_FLASH_SECT_SZ	/* Env sector Size */
-#endif
-/*==============================*/
-/* U-Boot general configuration */
-/*==============================*/
-#define CONFIG_MISC_INIT_R
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer sz */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CRC32_VERIFY
-#define CONFIG_MX_CYCLIC
-/*===================*/
-/* Linux Information */
-/*===================*/
-#define LINUX_BOOT_PARAM_ADDR	0x80000100
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTARGS		"mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTCOMMAND	"setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
-/*=================*/
-/* U-Boot commands */
-/*=================*/
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_SETGETDCR
-#ifdef CONFIG_SYS_USE_NAND
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#define CONFIG_CMD_NAND
-#elif defined(CONFIG_SYS_USE_NOR)
-#define CONFIG_CMD_JFFS2
-#else
-#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
-#endif
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
