From patchwork Fri Apr 3 18:40:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 458017 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0C98014012C for ; Sat, 4 Apr 2015 05:41:16 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=agner.ch header.i=@agner.ch header.b=ZTPeFnUq; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C25A14A04C; Fri, 3 Apr 2015 20:41:06 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id h9bFCPk9d2h7; Fri, 3 Apr 2015 20:41:06 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7A2CB392F; Fri, 3 Apr 2015 20:40:59 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 393F04A03B for ; Fri, 3 Apr 2015 20:40:53 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3EOMLGwsnUUA for ; Fri, 3 Apr 2015 20:40:53 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.kmu-office.ch (mail.kmu-office.ch [178.209.48.109]) by theia.denx.de (Postfix) with ESMTP id 0D2D94A036 for ; Fri, 3 Apr 2015 20:40:49 +0200 (CEST) Received: from trochilidae.agner.local (195-226-23-137.pool.cyberlink.ch [195.226.23.137]) by mail.kmu-office.ch (Postfix) with ESMTPSA id 61F565C0885; Fri, 3 Apr 2015 20:40:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=agner.ch; s=dkim; t=1428086402; bh=rRj5P+euPN3eXnGj/vaO2sNx+/Kz058FRww4emRhtTA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZTPeFnUqEulO38PYBxp2seHrGktnAHgW2c8TB2IBNk7tKbdpIfe85b+gd6vlYo2Ja u/UoOZ3uFnIiw1UkQG40+hHX7I2PS9nETj1Fmy1USh4WWxym2eeCQqdkGoXOvW9ium nuEMYpn2pmNdpb/eE0A8M1MZCUnrfHBf+aCeV8nM= From: Stefan Agner To: scottwood@freescale.com, trini@konsulko.com Date: Fri, 3 Apr 2015 20:40:44 +0200 Message-Id: <1428086445-10554-3-git-send-email-stefan@agner.ch> X-Mailer: git-send-email 2.3.5 In-Reply-To: <1428086445-10554-1-git-send-email-stefan@agner.ch> References: <1428086445-10554-1-git-send-email-stefan@agner.ch> Cc: u-boot@lists.denx.de, bpringlemeir@nbsps.com Subject: [U-Boot] [PATCH 3/4] mtd: vf610_nfc: add 32-error correction option for HW ECC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add option to choose between current 24-error correction and 32-error correction through Kconfig. 32-error correction allow to use NAND chips which require up to 8-bit error correction per 512 byte (when using 2K pages). Signed-off-by: Stefan Agner --- drivers/mtd/nand/Kconfig | 15 +++++++++++++++ drivers/mtd/nand/vf610_nfc.c | 38 ++++++++++++++++++++++++++++++++------ 2 files changed, 47 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 8056c06..ca14cc2 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -47,6 +47,21 @@ config SYS_NAND_BUSWIDTH_16BIT help Use 16-bit wide NAND flash interface. +choice + prompt "Hardware ECC strength" + depends on NAND_VF610_NFC + default SYS_NAND_VF610_NFC_45_ECC_BYTES + help + Select the ECC strength used in the hardware BCH ECC block. + +config SYS_NAND_VF610_NFC_45_ECC_BYTES + bool "24-error correction (45 ECC bytes)" + +config SYS_NAND_VF610_NFC_60_ECC_BYTES + bool "32-error correction (60 ECC bytes)" + +endchoice + if SPL config SPL_NAND_DENALI diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index 8608ac3..a8af00e 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -71,6 +71,7 @@ /* NFC ECC mode define */ #define ECC_BYPASS 0 #define ECC_45_BYTE 6 +#define ECC_60_BYTE 7 /*** Register Mask and bit definitions */ @@ -155,7 +156,10 @@ struct vf610_nfc { #define mtd_to_nfc(_mtd) \ (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv -static struct nand_ecclayout vf610_nfc_ecc45 = { +#if defined (CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES) +#define ECC_HW_MODE ECC_45_BYTE + +static struct nand_ecclayout vf610_nfc_ecc = { .eccbytes = 45, .eccpos = {19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, @@ -167,6 +171,24 @@ static struct nand_ecclayout vf610_nfc_ecc45 = { {.offset = 8, .length = 11} } }; +#elif defined (CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES) +#define ECC_HW_MODE ECC_60_BYTE + +static struct nand_ecclayout vf610_nfc_ecc = { + .eccbytes = 60, + .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 19, + 20, 21, 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32, 33, 34, 35, + 36, 37, 38, 39, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 49, 50, 51, + 52, 53, 54, 55, 56, 57, 58, 59, + 60, 61, 62, 63 }, + .oobfree = { + {.offset = 2, + .length = 2} } +}; +#endif static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg) { @@ -333,7 +355,7 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN, command, PROGRAM_PAGE_CMD_CODE); vf610_nfc_addr_cycle(mtd, column, page); - vf610_nfc_ecc_mode(mtd, ECC_45_BYTE); + vf610_nfc_ecc_mode(mtd, ECC_HW_MODE); break; case NAND_CMD_RESET: @@ -362,7 +384,7 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, NAND_CMD_READSTART, READ_PAGE_CMD_CODE); vf610_nfc_addr_cycle(mtd, column, page); - vf610_nfc_ecc_mode(mtd, ECC_45_BYTE); + vf610_nfc_ecc_mode(mtd, ECC_HW_MODE); break; case NAND_CMD_ERASE1: @@ -643,17 +665,21 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) goto error; } - chip->ecc.layout = &vf610_nfc_ecc45; - /* propagate ecc.layout to mtd_info */ mtd->ecclayout = chip->ecc.layout; chip->ecc.read_page = vf610_nfc_read_page; chip->ecc.write_page = vf610_nfc_write_page; chip->ecc.mode = NAND_ECC_HW; - chip->ecc.bytes = 45; chip->ecc.size = PAGE_2K; + chip->ecc.layout = &vf610_nfc_ecc; +#if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES) chip->ecc.strength = 24; + chip->ecc.bytes = 45; +#elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES) + chip->ecc.strength = 32; + chip->ecc.bytes = 60; +#endif /* Enable ECC_STATUS */ vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);