From patchwork Tue Mar 24 12:29:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 453807 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 8BDC51400A0 for ; Tue, 24 Mar 2015 23:30:21 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E9D534A047; Tue, 24 Mar 2015 13:30:17 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9Bhg3xavUgSl; Tue, 24 Mar 2015 13:30:17 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 508E74A029; Tue, 24 Mar 2015 13:30:17 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 807F44A029 for ; Tue, 24 Mar 2015 13:30:14 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ky7QvNnuxgsr for ; Tue, 24 Mar 2015 13:30:14 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) by theia.denx.de (Postfix) with ESMTPS id 10BF04A01F for ; Tue, 24 Mar 2015 13:30:10 +0100 (CET) Received: from localhost.localdomain ([46.140.72.82]) by mrelay.perfora.net (mreueus003) with ESMTPSA (Nemesis) id 0M4Iqr-1ZRWqZ0039-00rlLv; Tue, 24 Mar 2015 13:29:36 +0100 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Tue, 24 Mar 2015 13:29:14 +0100 Message-Id: <1427200154-9975-1-git-send-email-marcel@ziswiler.com> X-Mailer: git-send-email 1.9.3 X-Provags-ID: V03:K0:pel6lcQtXZFcgeGh7itDz0QBpcR27cB0gvCut5lAa0kHQW2Sa93 VDcHnUxR7cs519DvvXRoS/7Nmm+JOkOuw2QO8jM2h3MQtGLRN6Yy0lJIiIwr4AvKAefozEn Uy2mJn0rM85z2b8rjHYh4wxP1nyYSo6hF0qXrxfURVTK93J5rITSGBgf9UbM+AKxBVL2PuJ XcPD+uFvNmHcFarFIIqhw== X-UI-Out-Filterresults: notjunk:1; Cc: Stephen Warren , Tom Rini , Masahiro Yamada , Tom Warren , Marcel Ziswiler Subject: [U-Boot] [PATCH] tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BIT X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Lucas Stach Even the 8-bit case needs KBCB configured, as pin D7 is located in this pingroup. Also pingroup ATC seems to come out of reset with config set to NAND, so we need to explictly configure some other function to this group in order to avoid clashing settings. Signed-off-by: Lucas Stach Signed-off-by: Marcel Ziswiler Tested-by: Marcel Ziswiler --- arch/arm/mach-tegra/tegra20/funcmux.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c index 0df4a07..f9b6214 100644 --- a/arch/arm/mach-tegra/tegra20/funcmux.c +++ b/arch/arm/mach-tegra/tegra20/funcmux.c @@ -252,17 +252,25 @@ int funcmux_select(enum periph_id id, int config) break; case FUNCMUX_NDFLASH_KBC_8_BIT: pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); pinmux_tristate_disable(PMUX_PINGRP_KBCA); + pinmux_tristate_disable(PMUX_PINGRP_KBCB); pinmux_tristate_disable(PMUX_PINGRP_KBCC); pinmux_tristate_disable(PMUX_PINGRP_KBCD); pinmux_tristate_disable(PMUX_PINGRP_KBCE); pinmux_tristate_disable(PMUX_PINGRP_KBCF); + /* + * configure pingroup ATC to something unrelated to + * avoid ATC overriding KBC + */ + pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); + bad_config = 0; break; }