From patchwork Mon Feb 23 13:09:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 442467 X-Patchwork-Delegate: l.majewski@samsung.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9210314016B for ; Tue, 24 Feb 2015 00:13:34 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A25614A047; Mon, 23 Feb 2015 14:11:35 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id icrkmiOvDx5M; Mon, 23 Feb 2015 14:11:35 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B00284A050; Mon, 23 Feb 2015 14:11:34 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EEE984A020 for ; Mon, 23 Feb 2015 14:11:00 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Aw913xfLWVCe for ; Mon, 23 Feb 2015 14:11:00 +0100 (CET) X-policyd-weight: SBL_XBL_SPAMHAUS=ERR(-1.5) NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id 5AD614A02E for ; Mon, 23 Feb 2015 14:10:44 +0100 (CET) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id t1NDAX6w004802; Mon, 23 Feb 2015 07:10:33 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1NDAWOk029887; Mon, 23 Feb 2015 07:10:32 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Mon, 23 Feb 2015 07:10:32 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1NDAQfp012678; Mon, 23 Feb 2015 07:10:30 -0600 From: Kishon Vijay Abraham I To: , , , Date: Mon, 23 Feb 2015 18:39:44 +0530 Message-ID: <1424697023-26696-2-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1424697023-26696-1-git-send-email-kishon@ti.com> References: <1424697023-26696-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Cc: kishon@ti.com, nsekhar@ti.com, rogerq@ti.com Subject: [U-Boot] [u-boot PATCH v2 01/40] ARM: DRA7: Enable clocks for USB OTGSS and USB PHY X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enabled clocks for dwc3 controller and USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Lukasz Majewski --- arch/arm/cpu/armv7/omap5/hw_data.c | 14 ++++++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 10 +++++----- arch/arm/include/asm/omap_common.h | 4 ++-- 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 95f1686..9315bce 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -455,6 +455,10 @@ void enable_basic_clocks(void) (*prcm)->cm_l4per_gpio6_clkctrl, (*prcm)->cm_l4per_gpio7_clkctrl, (*prcm)->cm_l4per_gpio8_clkctrl, +#ifdef CONFIG_USB_DWC3 + (*prcm)->cm_l3init_ocp2scp1_clkctrl, + (*prcm)->cm_l3init_usb_otg_ss1_clkctrl, +#endif 0 }; @@ -486,6 +490,16 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); +#ifdef CONFIG_USB_DWC3 + /* Enable 960 MHz clock for dwc3 */ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Enable 32 KHz clock for dwc3 */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); +#endif + /* Set the correct clock dividers for mmc */ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_DIV_MASK); diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 0745d42..440bb40 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -575,7 +575,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_div_m2_dpll_unipro = 0x4a0081d0, .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, - .cm_coreaon_usb_phy_core_clkctrl = 0x4A008640, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640, .cm_coreaon_bandgap_clkctrl = 0x4a008648, .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, @@ -709,7 +709,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_fsusb_clkctrl = 0x4a0096d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, - .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0, + .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0, /* prm irqstatus regs */ .prm_irqstatus_mpu_2 = 0x4ae06014, @@ -801,8 +801,8 @@ struct prcm_regs const dra7xx_prcm = { .cm_clkmode_dpll_dsp = 0x4a005234, .cm_shadow_freq_config1 = 0x4a005260, .cm_clkmode_dpll_gmac = 0x4a0052a8, - .cm_coreaon_usb_phy_core_clkctrl = 0x4a008640, - .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, + .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, /* cm1.mpu */ .cm_mpu_mpu_clkctrl = 0x4a005320, @@ -908,7 +908,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, - .cm_l3init_usb_otg_ss_clkctrl = 0x4a0093f0, + .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0093f0, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009700, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 323952f..bd43099 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -143,7 +143,7 @@ struct prcm_regs { u32 cm_div_m2_dpll_unipro; u32 cm_ssc_deltamstep_dpll_unipro; u32 cm_ssc_modfreqdiv_dpll_unipro; - u32 cm_coreaon_usb_phy_core_clkctrl; + u32 cm_coreaon_usb_phy1_core_clkctrl; u32 cm_coreaon_usb_phy2_core_clkctrl; /* cm2.core */ @@ -230,7 +230,7 @@ struct prcm_regs { u32 cm_l3init_fsusb_clkctrl; u32 cm_l3init_ocp2scp1_clkctrl; u32 cm_l3init_ocp2scp3_clkctrl; - u32 cm_l3init_usb_otg_ss_clkctrl; + u32 cm_l3init_usb_otg_ss1_clkctrl; u32 prm_irqstatus_mpu_2;