From patchwork Fri Feb 20 12:43:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 441945 X-Patchwork-Delegate: yamada.m@jp.panasonic.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EFC1E140129 for ; Fri, 20 Feb 2015 23:44:36 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1FD334B58F; Fri, 20 Feb 2015 13:44:19 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oL8wpielr32I; Fri, 20 Feb 2015 13:44:19 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B8C034B612; Fri, 20 Feb 2015 13:43:56 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0DDBE4A02F for ; Fri, 20 Feb 2015 13:43:39 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gglo4V_1GFhn for ; Fri, 20 Feb 2015 13:43:38 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp.mei.co.jp (smtp.mei.co.jp [133.183.100.20]) by theia.denx.de (Postfix) with ESMTP id 2E1924A032 for ; Fri, 20 Feb 2015 13:43:35 +0100 (CET) Received: from mail-gw.jp.panasonic.com ([157.8.1.157]) by smtp.mei.co.jp (8.12.11.20060614/3.7W/kc-maile14) with ESMTP id t1KChTYP016542; Fri, 20 Feb 2015 21:43:29 +0900 (JST) Received: from epochmail.jp.panasonic.com ([157.8.1.130]) by mail.jp.panasonic.com (8.11.6p2/3.7W/kc-maili17) with ESMTP id t1KChUA13846; Fri, 20 Feb 2015 21:43:30 +0900 Received: by epochmail.jp.panasonic.com (8.12.11.20060308/3.7W/lomi14) id t1KChU8j011225; Fri, 20 Feb 2015 21:43:30 +0900 Received: from poodle by lomi14.jp.panasonic.com (8.12.11.20060308/3.7W) with ESMTP id t1KChU9t011172; Fri, 20 Feb 2015 21:43:30 +0900 Received: from beagle.diag.org (beagle.diag.org [10.184.179.16]) by poodle (Postfix) with ESMTP id 1B3D22740043; Fri, 20 Feb 2015 21:43:30 +0900 (JST) From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 20 Feb 2015 21:43:15 +0900 Message-Id: <1424436207-28775-5-git-send-email-yamada.m@jp.panasonic.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1424436207-28775-1-git-send-email-yamada.m@jp.panasonic.com> References: <1424436207-28775-1-git-send-email-yamada.m@jp.panasonic.com> Subject: [U-Boot] [PATCH v2 04/16] ARM: UniPhier: reset NAND core in SPL for non-NAND boot mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" For all the UniPhier SoCs so far, the reset signal of the NAND core is automatically deasserted after the PLL gets stabled. (The bit 2 of SC_RSTCTRL is default to one.) This causes a fatal problem on the NAND controller of PH1-LD4. For that SoC, the NAND I/O pins are not set up yet at the power-on reset except the NAND boot mode. As a result, the NAND controller begins automatic device scanning with wrong I/O pins and finally hangs up. Actually, U-Boot dies after printing "NAND:" on the console unless the boot mode latch detected the NAND boot mode. To work around this problem, reset the NAND core in SPL for non-NAND boot modes. If CONFIG_NAND_DENALI is enabled, the reset signal is deasserted again in U-Boot proper. At this time, I/O pins have been correctly set up, the device scanning should succeed. Signed-off-by: Masahiro Yamada --- Changes in v2: - Added arch/arm/cpu/armv7/uniphier/ph1-pro4/early_clkrst_init.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/early_clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/early_clkrst_init.c index b5a4623..4b17dc4 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/early_clkrst_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/early_clkrst_init.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include +#include #include #include @@ -14,7 +16,10 @@ void early_clkrst_init(void) /* deassert reset */ tmp = readl(SC_RSTCTRL); + tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; + if (spl_boot_device() != BOOT_DEVICE_NAND) + tmp &= ~SC_RSTCTRL_NRST_NAND; writel(tmp, SC_RSTCTRL); readl(SC_RSTCTRL); /* dummy read */