From patchwork Fri Feb 20 12:43:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 441949 X-Patchwork-Delegate: yamada.m@jp.panasonic.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2314C140129 for ; Fri, 20 Feb 2015 23:45:14 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EE1DC4B624; Fri, 20 Feb 2015 13:44:42 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WX_Tf_Z16caF; Fri, 20 Feb 2015 13:44:42 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 46F524B653; Fri, 20 Feb 2015 13:44:05 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B24334A01C for ; Fri, 20 Feb 2015 13:43:39 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1rXnyRkEN2Rx for ; Fri, 20 Feb 2015 13:43:39 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp.mei.co.jp (smtp.mei.co.jp [133.183.100.20]) by theia.denx.de (Postfix) with ESMTP id 982FD4A039 for ; Fri, 20 Feb 2015 13:43:36 +0100 (CET) Received: from mail-gw.jp.panasonic.com ([157.8.1.157]) by smtp.mei.co.jp (8.12.11.20060614/3.7W/kc-maile13) with ESMTP id t1KChUtG027491; Fri, 20 Feb 2015 21:43:31 +0900 (JST) Received: from epochmail.jp.panasonic.com ([157.8.1.130]) by mail.jp.panasonic.com (8.11.6p2/3.7W/kc-maili17) with ESMTP id t1KChUA13855; Fri, 20 Feb 2015 21:43:30 +0900 Received: by epochmail.jp.panasonic.com (8.12.11.20060308/3.7W/lomi11) id t1KChURK007153; Fri, 20 Feb 2015 21:43:30 +0900 Received: from poodle by lomi11.jp.panasonic.com (8.12.11.20060308/3.7W) with ESMTP id t1KChUqk007125; Fri, 20 Feb 2015 21:43:30 +0900 Received: from beagle.diag.org (beagle.diag.org [10.184.179.16]) by poodle (Postfix) with ESMTP id 8A6BA2740043; Fri, 20 Feb 2015 21:43:30 +0900 (JST) From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 20 Feb 2015 21:43:21 +0900 Message-Id: <1424436207-28775-11-git-send-email-yamada.m@jp.panasonic.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1424436207-28775-1-git-send-email-yamada.m@jp.panasonic.com> References: <1424436207-28775-1-git-send-email-yamada.m@jp.panasonic.com> Subject: [U-Boot] [PATCH v2 10/16] ARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is necessary to use the USB 3.0 host controllers on PH1-Pro4. Signed-off-by: Masahiro Yamada --- Changes in v2: None arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c | 15 +++++++++++++++ arch/arm/include/asm/arch-uniphier/sc-regs.h | 11 ++++++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c index fe9936a..f735a9c 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c @@ -14,6 +14,10 @@ void clkrst_init(void) /* deassert reset */ tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | + SC_RSTCTRL_NRST_GIO; +#endif #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_RSTCTRL_NRST_ETHER; #endif @@ -26,6 +30,13 @@ void clkrst_init(void) writel(tmp, SC_RSTCTRL); readl(SC_RSTCTRL); /* dummy read */ +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp = readl(SC_RSTCTRL2); + tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; + writel(tmp, SC_RSTCTRL2); + readl(SC_RSTCTRL2); /* dummy read */ +#endif + /* privide clocks */ tmp = readl(SC_CLKCTRL); #ifdef CONFIG_UNIPHIER_ETH @@ -34,6 +45,10 @@ void clkrst_init(void) #ifdef CONFIG_USB_EHCI_UNIPHIER tmp |= SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_STDMAC; #endif +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_CLKCTRL_CLK_USB31 | SC_CLKCTRL_CLK_USB30 | + SC_CLKCTRL_CLK_GIO; +#endif #ifdef CONFIG_NAND_DENALI tmp |= SC_CLKCTRL_CLK_NAND; #endif diff --git a/arch/arm/include/asm/arch-uniphier/sc-regs.h b/arch/arm/include/asm/arch-uniphier/sc-regs.h index daeeec9..397ace8 100644 --- a/arch/arm/include/asm/arch-uniphier/sc-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sc-regs.h @@ -1,7 +1,7 @@ /* * UniPhier SC (System Control) block registers * - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -38,19 +38,28 @@ #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) +#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) +#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) #define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) +#define SC_RSTCTRL_NRST_GIO (0x1 << 6) #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) #define SC_RSTCTRL_NRST_NAND (0x1 << 2) #define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) +#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) +#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) + #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) +#define SC_CLKCTRL_CLK_USB31 (0x1 << 17) +#define SC_CLKCTRL_CLK_USB30 (0x1 << 16) #define SC_CLKCTRL_CLK_ETHER (0x1 << 12) #define SC_CLKCTRL_CLK_MIO (0x1 << 11) #define SC_CLKCTRL_CLK_STDMAC (0x1 << 10) +#define SC_CLKCTRL_CLK_GIO (0x1 << 6) #define SC_CLKCTRL_CLK_UMC (0x1 << 4) #define SC_CLKCTRL_CLK_NAND (0x1 << 2) #define SC_CLKCTRL_CLK_SBC (0x1 << 1)