From patchwork Mon Feb 16 08:23:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Siamashka X-Patchwork-Id: 439980 X-Patchwork-Delegate: hdegoede@redhat.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 78996140190 for ; Mon, 16 Feb 2015 19:24:32 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 49F374B5CD; Mon, 16 Feb 2015 09:24:26 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZBDIvBUN6zcQ; Mon, 16 Feb 2015 09:24:25 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6FF5B4B576; Mon, 16 Feb 2015 09:24:25 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DBDDB4B576 for ; Mon, 16 Feb 2015 09:24:21 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Pz9Rfqy3fiZB for ; Mon, 16 Feb 2015 09:24:21 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-la0-f54.google.com (mail-la0-f54.google.com [209.85.215.54]) by theia.denx.de (Postfix) with ESMTPS id 94ACB4B150 for ; Mon, 16 Feb 2015 09:24:18 +0100 (CET) Received: by labpn19 with SMTP id pn19so26905875lab.4 for ; Mon, 16 Feb 2015 00:24:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=pRhntt8KPu6epyiLDdOI8mTUkZ7r5DCZIvqECqZQ5UU=; b=C9oGD3UpBDrzX6cS+OYqlpaAMx8ukSDHGUibwFz9V+xqP+FTyexhTnrZ9lEEHH3wxy 0joCnrTybM9xcyHyc1ZkoOD9At0cb3n/G+87bHXOthcdvtSjFVY/VSvt++PIgnSNUfRu /AnuqzRdqYZ1HOiyTWj1Bn/+oFD0Wg3qOKQnohYQ6bpMp0jCNMwelwPGvgL7UwYZi1RH TgYQQykDF8dn9aglNq3+2/UDVSSoGOiDBPqKTW0nATDyiKp7rSb3L+pmGyGwxJKsJ/lC b1VPpJ45vewRRnQrNsmmZy4lcswUvau8GbmFNg/bL25ogi5Npllg+14VYh4oheAZ0DRu 7syQ== X-Received: by 10.112.235.10 with SMTP id ui10mr4520267lbc.77.1424075058321; Mon, 16 Feb 2015 00:24:18 -0800 (PST) Received: from localhost.localdomain (85-76-73-164-nat.elisa-mobile.fi. [85.76.73.164]) by mx.google.com with ESMTPSA id g5sm2791215lag.11.2015.02.16.00.24.10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 16 Feb 2015 00:24:17 -0800 (PST) From: Siarhei Siamashka To: u-boot@lists.denx.de Date: Mon, 16 Feb 2015 10:23:59 +0200 Message-Id: <1424075039-19099-1-git-send-email-siarhei.siamashka@gmail.com> X-Mailer: git-send-email 2.0.5 Cc: Karsten Merker , Tom Rini , Ian Campbell Subject: [U-Boot] [PATCH] sunxi: Support the FEL boot mode in the regular u-boot build X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" So that the CONFIG_SPL_FEL option is not needed anymore. And the regular SPL binary, generated by the default u-boot build, is now also bootable over USB in the FEL mode. The SPL still can boot from the SD card too. A bunch of system registers need to be saved/restored in order to ensure that the IRQ handler still works in the BROM FEL code after getting control back from the SPL. This is done in the sunxi code instead of abusing ifdefs in 'start.S'. The decision whether to load the main u-boot binary from the SD card or return to the FEL code in the BROM is done at runtime. Signed-off-by: Siarhei Siamashka --- This patch needs to be applied after Simon's FEL patches: http://patchwork.ozlabs.org/patch/437580/ http://patchwork.ozlabs.org/patch/437581/ http://patchwork.ozlabs.org/patch/437582/ The CONFIG_SPL_FEL option can be still kept during the transition period. But we really need to get rid of this special CONFIG_SPL_FEL option as soon as possible. Because it is an extra maintenance burden and also introduces restrictions, such as the SPL size limit. Which hinders the addition of useful features to the SPL. arch/arm/cpu/armv7/sunxi/board.c | 35 +++++++++++++++++++++++++++++------ arch/arm/cpu/armv7/sunxi/fel_utils.S | 23 +++++++++++++++++++++++ 2 files changed, 52 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index b7492ac..c02c015 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -30,6 +30,10 @@ struct fel_stash { uint32_t sp; uint32_t lr; + uint32_t cpsr; + uint32_t sctlr; + uint32_t vbar; + uint32_t cr; }; struct fel_stash fel_stash __attribute__((section(".data"))); @@ -108,15 +112,34 @@ void s_init(void) */ u32 spl_boot_device(void) { +#ifdef CONFIG_SPL_FEL /* - * Have we been asked to return to the FEL portion of the boot ROM? - * TODO: We need a more robust test here, or bracket this with - * #ifdef CONFIG_SPL_FEL. + * This is the legacy compile time configuration for a special FEL + * enabled build. It has many restrictions and can only boot over USB. */ - if (fel_stash.lr >= 0xffff0000 && fel_stash.lr < 0xffff4000) + return BOOT_DEVICE_BOARD; +#else + /* + * When booting from the SD card, the "eGON.BT0" signature is expected + * to be found in memory at the address 0x0004 (see the "mksunxiboot" + * tool, which generates this header). + * + * When booting in the FEL mode over USB, this signature is patched in + * memory and replaced with something else by the 'fel' tool. This other + * signature is selected in such a way, that it can't be present in a + * valid bootable SD card image (because the BROM would refuse to + * execute the SPL in this case). + * + * This branch is just making a decision at runtime whether to load + * the main u-boot binary from the SD card (if the "eGON.BT0" signature + * is found) or return to the FEL code in the BROM to wait and receive + * the main u-boot binary over USB. + */ + if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */ + return BOOT_DEVICE_MMC1; + else return BOOT_DEVICE_BOARD; - - return BOOT_DEVICE_MMC1; +#endif } /* No confirmation data available in SPL yet. Hardcode bootmode */ diff --git a/arch/arm/cpu/armv7/sunxi/fel_utils.S b/arch/arm/cpu/armv7/sunxi/fel_utils.S index 0c1de52..e1b28a3 100644 --- a/arch/arm/cpu/armv7/sunxi/fel_utils.S +++ b/arch/arm/cpu/armv7/sunxi/fel_utils.S @@ -15,11 +15,34 @@ ENTRY(save_boot_params) ldr r0, =fel_stash str sp, [r0, #0] str lr, [r0, #4] + mrs lr, cpsr @ Read CPSR + str lr, [r0, #8] + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register + str lr, [r0, #12] + mrc p15, 0, lr, c12, c0, 0 @ Read VBAR + str lr, [r0, #16] + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register + str lr, [r0, #20] b save_boot_params_ret ENDPROC(save_boot_params) ENTRY(return_to_fel) mov sp, r0 mov lr, r1 +#ifndef CONFIG_SPL_FEL + /* + * The CONFIG_SPL_FEL build skips setting these registers, + * so there is no need to restore them here. + */ + ldr r0, =fel_stash + ldr r1, [r0, #20] + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register + ldr r1, [r0, #16] + mcr p15, 0, r1, c12, c0, 0 @ Write VBAR + ldr r1, [r0, #12] + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register + ldr r1, [r0, #8] + msr cpsr, r1 @ Write CPSR +#endif bx lr ENDPROC(return_to_fel)