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Fri, 13 Feb 2015 05:10:53 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BL2FFO11FD048.mail.protection.outlook.com (10.173.161.210) with Microsoft SMTP Server (TLS) id 15.1.87.10 via Frontend Transport; Fri, 13 Feb 2015 05:10:53 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t1D5AkS0004659; Thu, 12 Feb 2015 22:10:50 -0700 From: Alison Wang To: , , Date: Fri, 13 Feb 2015 13:08:15 +0800 Message-ID: <1423804095-17483-2-git-send-email-b18965@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1423804095-17483-1-git-send-email-b18965@freescale.com> References: <1423804095-17483-1-git-send-email-b18965@freescale.com> X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=b18965@freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(50226001)(50986999)(47776003)(2950100001)(105606002)(106466001)(104016003)(85426001)(92566002)(551934003)(229853001)(36756003)(2201001)(87936001)(50466002)(77096005)(33646002)(46102003)(19580395003)(6806004)(19580405001)(62966003)(77156002)(76176999)(450100001)(48376002)(107886001)(42262002); DIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR0301MB1290; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:CY1PR0301MB1290; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004); SRVR:CY1PR0301MB1290; X-Forefront-PRVS: 0486A0CB86 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:; SRVR:CY1PR0301MB1290; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2015 05:10:53.1014 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB1290 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:CY1PR0301MB1259; X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH 2/2] arm: ls102xa: Fix interleaving issue on CCI400 slave interface S2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" On silicon VER1.0, there is an interleaving issue on CCI400 slave interface S2. The workaround is to enable regulation of outstanding read transactions for slave interface S2. Signed-off-by: Alison Wang --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++ board/freescale/ls1021aqds/ls1021aqds.c | 7 +++++++ board/freescale/ls1021atwr/ls1021atwr.c | 7 +++++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 4b1cd3b..1a61d4a 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -463,6 +463,8 @@ struct ccsr_ddr { #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 #define CCI400_SNOOP_REQ_EN 0x00000001 +#define CCI400_REGULATION_READ_EN 0x00000008 +#define CCI400_INT_MAX_OUT_TRANS 0x01000000 /* CCI-400 registers */ struct ccsr_cci400 { diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index b6bba6c..93df046 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -217,6 +217,13 @@ int board_early_init_f(void) */ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + /* + * To fix interleaving issue on VER1.0, regulation of + * outstanding read transactions for slave interface S2 + * is enabled + */ + out_le32(&cci->slave[2].qos_ctrl, CCI400_REGULATION_READ_EN); + out_le32(&cci->slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS); /* Workaround for the issue that DDR could not respond to * barrier transaction which is generated by executing DSB/ISB diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index bd6068f..9101bd6 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -301,6 +301,13 @@ int board_early_init_f(void) */ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + /* + * To fix interleaving issue on VER1.0, regulation of + * outstanding read transactions for slave interface S2 + * is enabled + */ + out_le32(&cci->slave[2].qos_ctrl, CCI400_REGULATION_READ_EN); + out_le32(&cci->slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS); } return 0;